Zip CPU retweeted
Virginity at marriage used to be expected. Now it's mocked.
We've created a culture where a woman who saves herself is called repressed, and a woman who gives herself to dozens of men is called empowered.
But the data is clear: women who had zero sexual partners before marriage report the highest levels of marital satisfaction. Every additional partner before marriage statistically decreases the likelihood that the marriage will last.
The pair bonding that happens during physical intimacy is real. It's hormonal. It's designed to attach you to one person for life. Every time you bond and break, the mechanism weakens.
Your grandmother wasn't naive for saving herself. She was protecting something precious.
Replying to @alexschultz002
No need. I've already got a random number. 😆
Zip CPU retweeted
Lmao
Replying to @motaz_shokry
Just to nitpick, assembly has nothing to do with how processor works on an electrical level. Assembly language is the software side of things. You don't need to know anything about the cpu on an internal hardware level, to learn/use/master assembly.
Zip CPU retweeted
The RF world is insane.
Researchers recovered AES-128 keys from a Bluetooth chip by listening to its own antenna from 10 meters away.
Crypto-engine switching noise couples into the RF chain, rides the 2.4 GHz carrier, and leaks out as radio.
Zip CPU retweeted
Progress in science starts with one simple act:
telling the truth about what isn’t working.
Zip CPU retweeted
yeah, some may say Verilog is too low level, but think about Cray-1 supercomputer back in 70s, far before Verilog... in fact, the machine was a discrete "gate array" w/ 200k NAND gates, all wired by hand! real hardware is not much different... 🔥
computerhistory.org/revoluti…
If you are not doing hardware in Verilog or SystemVerilog, you are not a hardware designer.
If that triggers you, good.
Hardware is bits, timing, wires, and state. If you don’t love the low level, you don’t understand the machine.
The people in the 50s, 60s, 70s felt every bit. Seymour Cray. Robert Tomasulo. They built real systems.
And now people design “hardware” three abstractions away from silicon and call it engineering.
What happened?
Zip CPU retweeted
Replying to @1llegalEngineer @zipcpu
They fly so close to the silicon, they end up based and redpilled
Feel free to join the discussion of what makes an ideal memory controller on Reddit.
reddit.com/r/ZipCPU/comments…
Zip CPU retweeted
Almost forgot ... feel free to comment to this post on Reddit, at:
reddit.com/r/ZipCPU/comments…
Zip CPU retweeted
get into FPGAs.
they’re not as hyped as AI or robotics, but they’re the hidden backbone of both.
you want speed? determinism? ultra-low latency? hardware-level parallelism?
that’s FPGA territory.
every serious system; autonomous vehicles, defense tech, high-frequency trading, industrial control; runs faster because some engineer somewhere mastered reconfigurable logic.
software gives you flexibility.
hardware gives you performance.
FPGAs give you both.
learn VHDL or Verilog.
build a simple CPU.
implement a PID controller.
accelerate an ML inference.
you’ll suddenly see how computing really works; not just in code, but in electrons.
FPGAs are the bridge between hardware and software thinking. and if you can master that bridge, you become dangerous.
Zip CPU retweeted
Since I started doing logic design, programming feels like a joke. In logic design, you have to think in so many more dimensions and in parallel.
Zip CPU retweeted
I wonder how many Conservative speakers have stopped participating in Tech Conferences because of the politics?
Off the top of my head I can think of a dozen or so prominent speakers, who you’ll now never find on a conference schedule.
Replying to @LundukeJournal
I left the conference circuit right around 2018. I knew things had gotten ugly with cancellations of conservatives (like me). I had no idea that it had gotten to the level of death threats.
There should be no politics at tech conferences. None.
Zip CPU retweeted
Replying to @lel0uch_vb
Thank you, you are right, I grabbed the wrong section of the file. This would be where I see multiple drivers. Both STATUS and DATA appear multiply driven.
Zip CPU retweeted
I found this interesting post from @zipcpu and, of course, I tested it on DarkRISCV: I started with a small loop setting 0/1 and 8x unroll, default SoC setup (Harvard Arch, BRAM, etc) and got 11 clocks/loop and 4 blinks, resulting in 36MHz! 🔥
zipcpu.com/zipcpu/2019/02/09…
Zip CPU retweeted
For those who want to write 50MB/sec to a SDIOcard or read at that speed. All from the convenience of a PMOD adapter machdyne.com/product/microsd…
via Verilog
github.com/ZipCPU/sdspi































