Chisel/FIRRTL Hardware Compiler Framework
Joined August 2013
- Tweets255
- Following30
- Followers1.6K
- Likes202
Chisel retweeted
Do you have a cool project using or building on FireSim or Chipyard? Submit a talk to the First FireSim and Chipyard User/Developer *Workshop*, co-located with @ASPLOSConf 2023 on March 26, 2023! Learn more and submit your work here: fires.im/workshop-2023/
Chisel retweeted
Less than 24 hours until our FireSim, Chipyard, and Hammer tutorial at @ISCAConfOrg! As usual, in-person attendees will be given free @awscloud EC2 F1 instances to run these tools hands-on! 1/3
Join our tutorial on FireSim and Chipyard at @ISCAConfOrg on June 18th! Attendees will work hands-on with the Chipyard @RISC_V SoC generator and deploy fast FPGA-based simulations using FireSim on @awscloud EC2 F1 instances. Learn more: fires.im/isca-2022-tutorial/
Chisel retweeted
Local FPGA support (@XilinxInc U250) and distrib SW sims are coming to FireSim this week! @KarandikarSagar and @NayiriKr will cover these features at OSCAR 2022 at @ISCAConfOrg on Saturday. Thanks to great work by @davidbiancolin @abejgonza @TimSnyderATX! oscar-workshop.github.io/Pro…
Chisel retweeted
Get involved and learn more about @chisel_lang, check out the site at chisel-lang.org/ and @MartinSchoeberl free book at github.com/schoeberl/chisel-…. Also notebooks.gesis.org/binder/j… for an interactive lab.
Chisel retweeted
Join us next Tuesday, April 19 at the CHIPS Alliance Spring Event to hear from Jack Koenig, senior staff engineer at SiFive, and other industry experts on open innovation. #RISCV #NoLimits xitter.cf/CHIPSAlliance/status/1…
Mark your calendars, the CHIPS Alliance Spring Event is coming up! Join us for this free, virtual event on April 19 to hear about the latest in open source innovation. chipsalliance.org/workshops-…
Chisel retweeted
I'm glad to share our upcoming DATE-2022 paper titled "Twine: A Chisel Extension for Component-Level Heterogeneous Design". Twine is a Chisel HDL extension for heterogeneous design. Source code release is here: github.com/Twine-Umich/Twine, paper is here: bit.ly/3IrvV65.
Chisel retweeted
Happy to say I have a fully working C program running on ChiselV, my RV32I @risc_v processor. Wrote a simple library (like an Arduino) to access the GPIO and Timer. Can’t be more satisfied! 🎉
Now, on to having a serial interface!
#RISCV #ChiselV
github.com/carlosedp/chiselv…
Chisel retweeted
Thrilled that the sample program from “Digital Design and Computer Architecture” book by Sarah and David Harris now works on ChiselV, my RISC-V core!
Chisel is great to build and test hardware designs.
@risc_v @chisel_lang #RISCV
github.com/carlosedp/chiselv
Chisel retweeted
The @CHIPSAlliance Fall Workshop is starting shortly but there is still time to register. There are some great #RISCV presentations so don't miss it. events.linuxfoundation.org/c…
Chisel retweeted
Join Jack Koenig, Engineer at SiFive, for an update on next-gen SoC design using the Chisel hardware construction language at the @CHIPSAlliance workshop on October 12.
Learn more and register here: hubs.la/H0YYswk0
#riscv #sifive #opensource #chipdesign
Chisel retweeted
Don’t miss Jack Koenig of @SiFive's session “Chisel Advances for Next-gen SoC Designs” at the CHIPS Alliance Fall Workshop on Oct. 12. Check out the schedule and register today: bit.ly/2WNSrEb
Chisel retweeted
Can't wait for the workshop and @jackakattack session. I've been playing with the latest @chisel_lang version and it's amazing.
Don’t miss Jack Koenig of @SiFive's session “Chisel Advances for Next-gen SoC Designs” at the CHIPS Alliance Fall Workshop on Oct. 12. Check out the schedule and register today: bit.ly/2WNSrEb
Chisel retweeted
Don't miss my talk on new features in [upcoming] Chisel 3.5 next Tuesday (Oct. 12) at 8:45 am Pacific Time!
Don’t miss the upcoming CHIPS Alliance Fall Workshop, taking place Tuesday, Oct. 12. This free event will feature talks from @AlibabaGroup, @antmicro, @SiFive, @westerndigital and more. Check out the schedule and register today: bit.ly/3FgrRF8
Chisel retweeted
Just pushed ChiselBlink, my latest example/base project for creating @chisel_lang RTL project with @OlofKindgren FuseSoc.
All automated and running on containers so no dependency on local tools.
See a demo here: asciinema.org/a/405850
github.com/carlosedp/chisel-…
#FPGA #Containers
Chisel retweeted
Extremely happy to see our @chisel_lang design "Ibtida SoC" being mentioned by @jackakattack at the @CHIPSAlliance workshop. Happy to be the part of an awesome community! 😁
Chisel retweeted
Check out all of the interesting talks yesterday at the CHIPS Alliance workshop including my talk about recent work in @chisel_lang! My talk starts at 1:48:48, direct link here: youtu.be/bLfBFpACh2s?t=6528
Yesterday’s CHIPS Alliance Spring Workshop brought the open source community together to discuss milestones, progress, updates and more. #ICYMI you can check out the replay here: bit.ly/3dmOV7T
Chisel retweeted
Also started a Chisel generator for Fusesoc so @chisel_lang designs can be generated and use all Fusesoc goodness! I’ll submit a PR soon…
@OlofKindgren
Chisel retweeted
Some Highlights:
• Much better naming via compiler plugin
• Boolean expression inlining
• assert, assume, cover with SV emission
• Source locators in always blocks
• Annotations will no longer prevent deduplication
• No more unreachable branches in emitted if-else
Chisel v3.4.0 has been released! See the release notes here: github.com/freechipsproject/… and try it out on Scastie! scastie.scala-lang.org/LLVNO…
Chisel retweeted
I'm please to announce that after a month and a release misfire, @chisel_lang v3.4.0-RC3 is live! Lots of improvements/fixes from RC1. Try it out with this Scastie link that shows off two of the improvements in 3.4: scastie.scala-lang.org/A3mX5…