Full Stack Bug Developer. Texas Forever 🤘

People's Republic of Berkeley
Joined September 2008
Thank God for Longhorn Football -- TEXAS FIGHT!
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Can security escort Ted Cruz out of the stadium right this instant!!! #OSUvsTEX
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Big news from SiFive: We're launching five new RISC-V IPs in our 2nd Gen Intelligence lineup to accelerate AI — from far edge IoT to the data center! - X160 Gen 2 - X180 Gen 2 - X280 / X390 / XM Gen 2 Learn more 👉 sifive.com/press/new-x100-se… #NoLimits
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Mill v1.0.0 is out: a better build tool for #Java, #Scala, and #Kotlin. Check it out! mill-build.org/blog/13-mill-…
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It's absolutely crazy to me that the most exciting Scala projects today are actually happening in the hardware RISC-V space with tools like Chisel rather than the traditional, stronghold domains. And, on top of that, they innovate in chip design.
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For anyone looking, this is the Tsunami risk map for San Francisco on sf72.org
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GREAT DAY TO BE A LONGHORN 🤘
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.@ElectronicDesgn shares more on the HiFive Premier P550 development board, featuring a quad-core #RISCV SoC, Imagination GPU, and ESWIN NPU, built for next-gen embedded development. Read all about it: hubs.la/Q02VN2Lc0 #NoLimits
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“If you’re looking to push the boundaries of what’s possible with RISC-V, this could be the test and development platform you’ve been waiting for.” Dave Altavilla shares his take on the SiFive HiFive Premier P550 development board here: hubs.la/Q02VN58C0 #NoLimits
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📢 The SiFive HiFive Premier P550 development boards are now shipping! Grab one from the initial pre-release batch of 100 Yocto-ready boards via @ArrowGlobal, or wait for the Ubuntu-supported version coming in Q4. Learn more: hubs.la/Q02V6v7H0 #RISCV #NoLimits
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DeepComputing is showing an early demo of the new RISC-V Mainboard at the @risc_v Summit in Munich next week. This board uses a @StarFiveTech JH7110 with @SiFive RISC-V CPU cores. DeepComputing is also working closely with the teams at @ubuntu and @fedora on Linux support.
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📢 New board alert! The HiFive Premier P550 is the highest performance #RISCV development board in the industry. Available through @ArrowGlobal this board enables developers to test & develop new RISC-V applications. Learn more here: hubs.la/Q02sgxc80 #NoLimits
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Watch talks from members on collaborative #opensource projects including Open Se Cura, #Caliptra RoT, #Chipyard, #UVM testbenches in #Verilator & using #FuseSoC w/ VeeRwolf: youtube.com/watch?v=_FUw1_f3… @linuxfoundation @risc_v @Google @antmicro @verisilicon @UCBerkeley @OlofKindgren
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Join the hybrid CHIPS Alliance Technology Update hosted by @Google for talks on #openhardware & collaborative #ASIC / #FPGA development by @intel, @westerndigital, @antmicro, @SiFive and @UMich, following #60DAC. Register: events.linuxfoundation.org/c… @risc_v @linuxfoundation @60thDAC
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We are delighted to hear that Chipyard, an open source framework for agile development of Chisel-based SoCs developed at UC Berkeley, supports several cores from PULP ecosystem. youtu.be/pYyv8BJ5n68?t=308 github.com/ucb-bar/chipyard chipyard.readthedocs.io/en/s…
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