No longer active here. Moved to other similar platforms
Joined November 2011
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Kick-out-the-nazis-from-our-online-communities-day is coming up in less than a week. But since this platform is nowadays run by such people I will choose to let myself out instead. You can easily find me on other similar platforms if you want to hear about SERV and FuseSoC.
Olof Kindgren retweeted
Second week of November and we have a brand new El Correo Libre for you all. This time we will learn about creating graphics on FPGA with @WillFlux, see @ATaylorFPGA having fun with FuseSoC, take a peek at @tnt's ROM compiler and much more. Enjoy!
fossi-foundation.org/blog/20…
Olof Kindgren retweeted
Professional FPGA development uses scripting more often than it uses a GUI. I just created a Hackster project which looks at using FuseSoC to build projects using scripts and enabling rapid targeting of FPGAs.
#fpga #embeddedsystems #electronics #embeddedsoftware #engineering
hackster.io/adam-taylor/fun-…
The illustrious @ATaylorFPGA just released an article on @Hacksterio on how to get started with FuseSoC. hackster.io/adam-taylor/fun-… An excellent read and highly recommended for anyone looking for a well-written and straight to the point FuseSoC introduction. Thanks Adam!
Olof Kindgren retweeted
Introducing Oasis: the first playable AI-generated game.
We partnered with @DecartAI to build a real-time, interactive world model that runs >10x faster on Sohu. We're open-sourcing the model architecture, weights, and research.
Here's how it works (and a demo you can play!):
Olof Kindgren retweeted
Altera "Logic Elements" are roughly comparable to AMD's "System Logic Cells." This makes things simpler. I'm perplexed by Lattice's "System Logic Cells." Using the same terminology with a different definition is confusing. CoreScore by @OlofKindgren is more meainingful.
Comparing the capacity of FPGAs with different architectures can be complicated.
Did you know you can fit 18 Very Efficient & Elegant RISC-V cores from the @CHIPSAlliance in a single Agilex™ 5 E-Series FPGA?
Read the whitepaper to learn more: intel.ly/3C0EI0I
Phew! That took longer than expected, but now FuseSoC 2.4 is finally released. As always, there's a number of bug fixes and convenience features. The big new feature is EDAM filter functions which you can read about in the docs fusesoc.readthedocs.io/en/la…
Enjoy!
Olof Kindgren retweeted
Did you catch the news about the flexible RISC-V processor developed by @Pragmatic_ltd's Emre Ozer, a longtime HiPEAC member, and others? Check out this short video of this exciting new development here: youtube.com/watch?v=m8dJAZST…
Congratulations to everyone involved in this work!
@OlofKindgren | @qamcom | @risc_v
I just updated the award-winning video gallery with the latest FuseSoC video from ORConf.
award-winning.me/videos/
And what's more important, I managed to fix the CSS after spending like four hours trying to make two div thingies the same height.
Olof Kindgren retweeted
#FPGA 1st Soft RISC-V Systems Workshop:
Thu Nov. 7 & Fri Nov. 8, 8am-12pm PDT, the @risc_v Soft CPU SIG is hosting a free online workshop & celebration of the vibrant RISC-V soft processor community.
RT/spread the word & join us as attendee or presenter.
sites.google.com/view/srvs-w…
Happy to finally reveal a project that @qamcom, @Harvard and @Pragmatic_ltd have worked on for the past two years, creating the first ever fully programmable, general-purpose SoC on printed electronics. And yes, of course it uses the award-winning SERV! :) qamcom.com/nature-article-be…
Olof Kindgren retweeted
And in response to the burning question on everyone's mind, we now know that you can fit 1327 RISC-V cores in a single Agilex 5 device thanks to corescore.store/ also by @OlofKindgren
Olof Kindgren retweeted
Of course it is also available on the obligatory FuseSoC Blinky project by @OlofKindgren
github.com/fusesoc/blinky
Olof Kindgren retweeted
You can also run the VeeRwolf reference platform from @CHIPSAlliance on Agilex 5. In fact you can run 18 of them on it if you go to the VeeRwolves branch.
github.com/chipsalliance/Vee…
Olof Kindgren retweeted
With this LiteX port by @enjoy_digital you can now run Linux on a soft RISC-V core on Agilex 5
github.com/enjoy-digital/lit…
Olof Kindgren retweeted
@AlteraFPGA_ Agilex 5 is making its way into open-source projects so you have even more examples and resources to help you get started. Let's look at a few (thread)
Olof Kindgren retweeted
Agilex 5 was recently added to the CoreScore leaderboard at 1327 SERV cores.
SERV is a tiny bit-serial #RISCV core developed by @OlofKindgren intel.ly/3ZlZGRq
#opensource #RISCV