@efabless

ASIC DESIGN REDEFINED

 Palo Alto, CA
efabless.com
Joined April 2013
  • Tweets1.5K
  • Following497
  • Followers3.6K
258Media
Chip Industry Week in Review Cheaper EUV; Applied's funding; export rule changes; semi equipment report; chip earnings; Alphawave’s UCIe die-die IP; Lams new cryo etch; Noyce award; chiplets &... semiengineering.com/chip-ind… #semiconductor #lithography @OISTedu #chiplets @imec_int

Chip Industry Week in Review

Cheaper EUV; Applied Materials funding issues; export rule changes; semi equipment report; chip industry earnings releases; Alphawave's UCIe die-die IP; Lams new cryo etch; Noyce award.

semiengineering.com
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It's been a long time coming, but I finally have the world’s first certified open source ASIC hardware project as a kit you can buy! store.tinytapeout.com/produc… For every kit sold, I will donate $100 to @oshwassociation More info: bit.ly/vga-asic-clock

TT03p5 Development Kit + VGA PMOD

This limited edition, special pack consists of the TT3.5 chip, demo board and VGA clock PMOD. This item is now offered at a discounted price, and as a result, it is no longer part of our Open Source...

store.tinytapeout.com
Matthew Venn@matthewvenn31 Mar 2022
Still can't quite believe I have a clock on my desk that is powered by a chip I designed!
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Replying to @WeebitNano
@WeebitNano and @efabless Corporation collaborate to enable easy, affordable prototyping of innovative SoC designs readmagazine.com/industries/… #ChipDesign #Efabless #news #prototyping #ReadMagazine #Semiconductorandelectronics #WeebitNano

Weebit Nano and Efabless collaborate to enable easy, affordable prototyping of innovative SoC...

Weebit Nano and Efabless Corporation announce their collaboration to enable fast and easy prototyping of intelligent devices

readmagazine.com
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EPDT@EPDTNEWS26 May 2024
Replying to @efabless
@efabless has announced a cooperative partnership with @WeebitNano. Aimed at bringing greater non-volatile memory (NVM) data storage capabilities to resource-constrained items of electronics hardware, such as wearables and IoT nodes, this will.. READ MORE epdtonthenet.net/article/205…
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DigiKeyEU@DigiKeyEU23 May 2024
💻🔬Efabless ermöglicht es Einzelpersonen, individuelle Chips zu entwerfen. Entdecken Sie interaktive Lernwerkzeuge und Plattformen wie chipIgnite, um den Prozess der Chip-Erstellung zu beherrschen. @efabless dky.bz/4ak3MLI #Chip #Innovation
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Olof Kindgren@OlofKindgren7 May 2024
I was the lucky winner of a @tinytapeout slot in the @efabless raffle at @LatchUpConf last month. In true yak shaving fashion this means I'm now busy creating a TT backend for Edalize so I can add a TT target to my SERV core description file and run through FuseSoC. Stay tuned...
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Finally, after a year from the submission my 1st #ASIC arrived. It is a real pleasure to be part of @TinyTapeout Run 3. Thank you @matthewvenn and @efabless for this opportunity. #openASICs #VLSI #sky130 #opensource #semiconductors
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Riscure's @jzvw designed a chip and taped out on Sky130, then decapped it and sniffed the AES keys with a near field probe! We talk about it in the next Efabless webinar: efabless.zoom.us/webinar/reg…
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I threw a quick test for Z80 tapeout using existing open-source core TV80: 1) CMOS 130nm via #TinyTapeout 07 / @efabless #ChipIgnite 2) ~4K logic gates 3) fits in 0.064 mm^2 ~ roughly 4 TT tiles 4) according to sim should run at 48 MHz Check it out: github.com/rejunity/z80-open…
ReJ 𓀨 Renaldas Zioma@__ReJ__21 Apr 2024
Now, open-source silicon-proven Z80 clone would be a worthy project for #TinyTapeout 07. It opens tomorrow and we have 6 weeks :) Shouldn’t be hard with existing HDL open-source clones & die-shots of Z80.
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Efabless releases OpenLane version 2, a major step forward in the evolution of open-source electronic design automation tools @efabless #electronics #design #Semiconductors newelectronics.co.uk/content…
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We were reviewed by @HackSpaceMag and got 10/10! "Learn how microchips work by designing one." Thanks to @efabless and all our supporters for making this possible! Read the full review here: hackspace.raspberrypi.com/is…
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DigiKey
@digikey9 Apr 2024
Unlocking the Tiny Titans: Why Chip Making Matters (and How Efabless Can Help You Rule the Chip Game) More here: dky.bz/4ahYVeV 📷 @efabless
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Replying to @matthewvenn @efabless
I really have loved watching this effort evolve. One day my skills and need will converge to the point that I will be able to take advantage of this!
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Following on from my oscillator xitter.cf/matthewvenn/status/176… I've now done the layout! Top graph is the simulated schematic and the bottom shows the simulated layout. The extra parasitic resistance and capacitance slows it down slightly. github.com/mattvenn/tt06-ana…
Matthew Venn@matthewvenn17 Mar 2024
It took about 10 hours of work, but I finally managed to get my relaxation oscillator to do its thing! Next step is layout for #TinyTapeout 6! Check the circuit with @UriShaked browser based xschem viewer: xschem-viewer.com/?file=http…
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#TinyTapeout 6 is closing in 37 days! Get your first #ASIC design started at tinytapeout.com/
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SemiWiki@DanielNenni11 Mar 2024
No! TSMC does not make 90% of advanced silicon semiwiki.com/semiconductor-m… #10nm #3DNAND #3nm #5nm #7nm #Dram #Intel #Logic #Samsung #Tsmc

No! TSMC does not Make 90% of Advanced Silicon

From figure 1 it can be seen that TSMC only represents 12% of worldwide “advanced silicon”, way off the 90% number being thrown around.

semiwiki.com
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LogicAnalyzer: a Raspberry Pi Pico-based 24 channel logic analyzer buff.ly/3T9sMyV
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AI/ML Challenges In Test and Metrology: The integration of AI/ML into semiconductor test & metrology is redefining the landscape for chip fabrication semiengineering.com/ai-ml-ch… #semiconductor #AIML #metrology #semiconductortest

AI/ML Challenges In Test and Metrology

New tools are changing the game, but it will take time and collaboration for them to achieve their full potential.

semiengineering.com
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cy384@cy38417 Feb 2024
it's alive! my humble four bit adder with 7 segment display is #120 on the tiny tapeout 2 chip! what an amazing opportunity
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STA is the #ASIC terminology of the week! zerotoasiccourse.com/termino… In the last month, STA has been the 11th most popular out of 42 terms.

www.zerotoasiccourse.com

Static Timing Analysis (STA) verifies that all data paths in a design meet setup and hold timing requirements without simulating every input combination, catching violations that could make a chip...

zerotoasiccourse.com
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