Andreas Abel (@uops_info) header
Andreas Abel (@uops_info) profile picture
Zürich, Switzerland
Joined March 2014
Photo by Andreas Abel (@uops_info)Photo by Andreas Abel (@uops_info)Photo by Andreas Abel (@uops_info)Photo by Andreas Abel (@uops_info)Photo by Andreas Abel (@uops_info)Photo by Andreas Abel (@uops_info)Photo by Andreas Abel (@uops_info)
I have added latency, throughput, and port usage data for Emerald Rapids, Meteor Lake, Arrow Lake, and Zen 5 to uops.info/table.html.
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Andreas Abel retweeted
Facile: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction arxiv.org/abs/2310.13212 IEEE International Symposium on Workload Characterization (IISWC) 2023 Andreas Abel (@uops_info), Shrey Sharma, Jan Reineke
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Latency, throughput, and port usage data for #Zen4 is now available at uops.info/table.html
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Good feature of uops.info: "URL" button in the top right corner gets you a URL that preserves the state of the table you've selected (which can be slowish to reconstruct). I was too dim to notice this! Thanks @uops_info for pointing this feature out.
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Andreas Abel retweeted
The entire #Intel Atom fleet appeared on uops.info site! Congratulations, @uops_info!
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nanoBench now has the option to perform cycle-by-cycle measurements, similar to @gamozolabs' Sushi Roll technique (xitter.cf/gamozolabs/status/1163…) github.com/andreas-abel/nano…
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Andreas Abel retweeted
#Intel released the 76th edition of the Software Developer’s Manuals with fixes, clarifications and #AlderLake intel.com/content/www/us/en/…
#Intel released the 75th edition of the Software Developer’s Manuals with #RocketLake mention, fixes, clarifications All-in-1: software.intel.com/content/w… Change: software.intel.com/content/w… (Oddly enough RKL CPUID 06_A7h isn't mentioned anywhere)
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Latency, throughput, and port usage data for Alder Lake is now available at uops.info/table.html. #Intel #AlderLake (1/4)
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mov, and lea instructions. However, it only works with 64-bit registers. It also only works for immediates < 1024; the immediate value influences how many adds can be eliminated per cycle. If an add is followed by an instruction that reads the flags, it is not eliminated. (3/4)
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A rather strange finding is that the ROR and ROL (with immediate) instructions require 1 uop if the registers {al, bl, cl, dl, r8b-r11b} are used, but for the registers {dil, sil, bpl, spl, r12b-r15b} (which have the same register numbers as the high8 registers), 3 uops are used.
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Part 2 of the follow-up to the "Simple Code" lecture is now available. In it, I show how to look through the compiled code using Compiler Explorer, then simulate its scheduling on Intel CPUs using UICA: youtu.be/1tEqsQ55-8I
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On Cascade Lake with a recent microcode update (0x5003102), the loop stream detector (LSD) appears to be disabled. With the older microcode 0x5002f01, the LSD is enabled.
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Today, I released uiCA, the "uops.info Code Analyzer". uiCA is based on data from uops.info, combined with a new detailed pipeline model. An online version (that also supports other tools) is available at uica.uops.info/ (1/3)
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You can find more information on uiCA in the following paper: arxiv.org/pdf/2107.14210.pdf xitter.cf/Underfox3/status/14210…
Researchers have developed a new simulator to predict the throughput of basic blocks of all Intel Core μarchs released in the last decade, demonstrating to be more accurate than the predictions of state-of-the-art tools by more than an order of magnitude. arxiv.org/pdf/2107.14210.pdf
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Latency, throughput, and port usage data for Rocket Lake is now available at uops.info/table.html
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The data shows that 'move elimination' is active on Rocket Lake, so the ICL065 issue appears to be fixed. xitter.cf/uops_info/status/13679…
I just noticed that with a recent microcode update, #Intel Ice Lake CPUs don't perform 'move elimination' any more for GPR registers. This is probably related to the ICL065 erratum (intel.de/content/www/de/de/p…).
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I have added data for Tiger Lake and Zen 3 to uops.info/table.html
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