@Underfox3

Physicist, Telecom Engineering lover, HPC Enthusiast. Prog Rock/Metal fan

underfox3.substack.com/
Joined December 2017
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Researchers have developed a new simulator to predict the throughput of basic blocks of all Intel Core μarchs released in the last decade, demonstrating to be more accurate than the predictions of state-of-the-art tools by more than an order of magnitude. arxiv.org/pdf/2107.14210.pdf
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After a long time, I’m finally on vacation, taking the opportunity to rest my mind from all the AI ​​noise. If the world ends or the bubble bursts while I’m away, just know that I’m happily fishing in the ocean and enjoying life. See you soon. 🦊 youtube.com/watch?v=vJXCgHG6…

Mike Soar - A Sailor's Life

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@Underfox3Sep 3
In this paper is introduced the first auto-tuning framework for Julia GPU kernels as an accessible Julia package, enabling systematic auto-tuning of hardware-agnostic kernels to target a wide variety of platforms, such as NVIDIA, AMD, Intel, and Apple. arxiv.org/pdf/2608.21227
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In this paper is presented CHIPSMORE, a multi-mode and multi-request CIM accelerator for LLM inference across diverse operating scenarios, including base-mode execution, LoRA adaptation, varying context lengths, and concurrent multi-request serving. arxiv.org/pdf/2608.30509
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Finally, a non-replicated multi-request execution pipeline exploits request-level parallelism without duplicating pretrained weights, while a state-aware resource reconfiguration mechanism selectively retains runtime states and power-gates inactive resources.
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The simulation results show that CHIPSMORE achieves up to 2.38× higher throughput and 27× higher energy efficiency on Mistral-7B inference compared with Nvidia H100 while eliminating weight replication for multi-request serving.
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In this paper is introduced the first auto-tuning framework for Julia GPU kernels as an accessible Julia package, enabling systematic auto-tuning of hardware-agnostic kernels to target a wide variety of platforms, such as NVIDIA, AMD, Intel, and Apple. arxiv.org/pdf/2608.21227
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The evaluation results on a GPU kernel in the NextLA linear algebra library show that this approach achieve performance improvements of 3× to 7× over median parameter configurations.
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@Underfox3Sep 2
[Basic Concepts] In this paper is presented a comprehensive and critical overview of on-chip photonic neural networks, spanning fundamental device technologies, system architectures, and emerging applications. advanced.onlinelibrary.wiley…
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@Underfox3Sep 2
In this paper is proposed GapFill, a specialized tool designed to assist professional anime colorists in addressing small, unpainted areas, integrating seamlessly into existing professional workflows. arxiv.org/pdf/2609.00800
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@Underfox3Sep 2
In this paper, AMD researchers have presented the first micro-architecture based performance characterization of SPEC CPU 2026 on AMD EPYC "Zen 5" processor. arxiv.org/pdf/2609.01527
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@Underfox3Sep 2
Researchers have presented the first experimental ML-enabled Process-Technology Co-Optimization (PTCO) framework for optimizing 2D TMD FET fabrication directly from statistically meaningful experimental data rather than pure simulation data. arxiv.org/pdf/2609.00722
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@Underfox3Sep 3
In this paper is proposed NeuroPrefetcher, a storage-backed sparse inference runtime built around predictive delta prefetching for the regime where an LLM exceeds resident memory throughout execution. arxiv.org/pdf/2608.22643
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In this paper is proposed NeuroPrefetcher, a storage-backed sparse inference runtime built around predictive delta prefetching for the regime where an LLM exceeds resident memory throughout execution. arxiv.org/pdf/2608.22643
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NeuroPrefetcher makes weight movement explicit, predicting which sparse weights the next token will need, compares that predicted set against the weights already resident, and fetches only the difference in advance.
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The evaluation results show that, in the memory-constrained regime, NeuroPrefetcher achieves 7.9–12.0x speedup over llama.cpp by replacing page-fault-driven whole-weight movement with application-scheduled sparse-row reads.
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Researchers have presented the first experimental ML-enabled Process-Technology Co-Optimization (PTCO) framework for optimizing 2D TMD FET fabrication directly from statistically meaningful experimental data rather than pure simulation data. arxiv.org/pdf/2609.00722
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These metrics are integrated into a multi-objective ranking framework and coupled with GPR to identify process–performance correlations and predict unexplored fabrication recipes within the experimental process space.
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The experimental results shows close agreement with ML predictions, thus demonstrating the framework’s ability to efficiently guide gatestack optimization through iterative experimental feedback.
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