Deep Insights For The Tech Industry #semiconductor #semiEDA #AI #embedded #verification #lowpower #test #DataAnalytics #automotive #chipdesign #ICmanufacturing
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Joined September 2013
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Scaling Data Movement For Physical AI youtu.be/tt5Xcjf9MVo?si=5V5x…
#PhysicalAI #chiplets #CPU #datamovement
#chiplets @arteris_noc #coherency #semiconductor
Agentic workloads increase CPU demand, while reasoning models, MoE architectures, and reservoir computing fuel AI acceleration.
semiengineering.com/agentic-…
#CPU #GPU #AgenticAi #semiconductor
Semiconductor Engineering retweeted
Semiconductor fabs are leveraging AI/ML models & raw equipment data to speed up yield learning, but the volume of data they are collecting is forcing some tough decisions about optimization versus context.
semiengineering.com/shift-le…
#semiconductor #fabs
Why Open-Weight AI Matters semiengineering.com/why-open…
Proprietary models still hold the edge, but open-weight models add more flexibility for deploying AI.
#openweightAImodels #AImodels #AI
Special Report: Why Physical AI Is So Hard To Engineer
semiengineering.com/why-phys…
#physicalAI #sensors #chipdesign
Semiconductor Engineering retweeted
Fab expansion accelerates; China advances memory & EUV; Teradyne’s test deal; SEMICON West & OCP highlights; 3D SiP; TSMC & ASML signals; 300mm fab spending; optical & 3nd D-compute startups funding; quantum HW ... semiengineering.com/chip-ind…
#semiconductor #lithography #DRAM
Semiconductor Engineering retweeted
Larger packages, finer routing, and embedded functions are pushing advanced substrates toward application-specific designs.semiengineering.com/one-subs…
#semiconductor #substrates #advancedpackaging #GlassSubstrates
Fab expansion accelerates; China advances memory & EUV; Teradyne’s test deal; SEMICON West & OCP highlights; 3D SiP; TSMC & ASML signals; 300mm fab spending; optical & 3nd D-compute startups funding; quantum HW ... semiengineering.com/chip-ind…
#semiconductor #lithography #DRAM
Semiconductor Engineering retweeted
80 chip industry-related startups raised $8.5B in Q3, with big hauls by companies tackling data movement and memory. semiengineering.com/startup-…
#semiconductor #startupfunding
Semiconductor fabs are leveraging AI/ML models & raw equipment data to speed up yield learning, but the volume of data they are collecting is forcing some tough decisions about optimization versus context.
semiengineering.com/shift-le…
#semiconductor #fabs
CPO Testing Faces A Moving Target Problem
semiengineering.com/cpo-test…
Test vendors adapt to changing connector architectures & extreme alignment tolerances as CPO heads toward mainstream
#CPO #CPOtest #NPO @Teradyneinc #Advantest
@aseglobal @Keysight #semiconductor #datacenter
Semiconductor Engineering retweeted
No single test, inspection, model, or monitoring technique provides a complete view of an advanced device. Each has physical, spatial, temporal, or contextual blind spots. semiengineering.com/closing-…
#semiconductor
80 chip industry-related startups raised $8.5B in Q3, with big hauls by companies tackling data movement and memory. semiengineering.com/startup-…
#semiconductor #startupfunding
Semiconductor Engineering retweeted
Latest: $2B foundry pact; hyper-NA EUV; TSMC, Samsung $; Canon's nanoimprint; AI chips under scrutiny; $10T data center buildout; $1.5B SiC boost; chip smuggling; 800V power; quantum HW scales up; mobile fab... semiengineering.com/chip-ind…
#semiconductor #semiEDA
Semiconductor Engineering retweeted
The shift from software-defined to AI-defined vehicles raises questions about whether the hardware can keep up.
semiengineering.com/ai-defin…
#automotive #SDVs #AIdefinedvehicles
Semiconductor Engineering retweeted
Increasing power density makes heat, stress, and aging harder to predict, and more critical to address earlier in the design. Part 2.
semiengineering.com/thermal-…
#semiconductor #photonics #thermal #AIchips
Latest: $2B foundry pact; hyper-NA EUV; TSMC, Samsung $; Canon's nanoimprint; AI chips under scrutiny; $10T data center buildout; $1.5B SiC boost; chip smuggling; 800V power; quantum HW scales up; mobile fab... semiengineering.com/chip-ind…
#semiconductor #semiEDA
No single test, inspection, model, or monitoring technique provides a complete view of an advanced device. Each has physical, spatial, temporal, or contextual blind spots. semiengineering.com/closing-…
#semiconductor
Semiconductor Engineering retweeted
The imec report: Towards scalable sCFET standard cell architectures: split-gate devices, a 5T+1 CFET SRAM bit cell, and improved back-end-of-line routability [Part 2] semiengineering.com/advancin…
#CFETs @imec_int #semiconductor #sCFETs #mCFET #SRAM
Semiconductor Engineering retweeted
Specialization and orchestration are becoming more important as the role of AI agents in chip design widens, but coordination, control, and trust remain challenging semiengineering.com/when-ai-…
#semiEDA #AgenticAI #chipdesign #semiconductor
