
Deep Insights For The Tech Industry #semiconductor #semiEDA #AI #embedded #verification #lowpower #test #DataAnalytics #automotive #chipdesign #ICmanufacturing
Silicon Valley
Joined September 2013
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Semiconductor Engineering retweeted
Semiconductor fabs are leveraging AI/ML models & raw equipment data to speed up yield learning, but the volume of data they are collecting is forcing some tough decisions about optimization versus context.
semiengineering.com/shift-le…
#semiconductor #fabs
Semiconductor Engineering retweeted
Fab expansion accelerates; China advances memory & EUV; Teradyne’s test deal; SEMICON West & OCP highlights; 3D SiP; TSMC & ASML signals; 300mm fab spending; optical & 3nd D-compute startups funding; quantum HW ... semiengineering.com/chip-ind…
#semiconductor #lithography #DRAM
Semiconductor Engineering retweeted
Larger packages, finer routing, and embedded functions are pushing advanced substrates toward application-specific designs.semiengineering.com/one-subs…
#semiconductor #substrates #advancedpackaging #GlassSubstrates
Semiconductor Engineering retweeted
80 chip industry-related startups raised $8.5B in Q3, with big hauls by companies tackling data movement and memory. semiengineering.com/startup-…
#semiconductor #startupfunding
Semiconductor Engineering retweeted
No single test, inspection, model, or monitoring technique provides a complete view of an advanced device. Each has physical, spatial, temporal, or contextual blind spots. semiengineering.com/closing-…
#semiconductor
Semiconductor Engineering retweeted
Latest: $2B foundry pact; hyper-NA EUV; TSMC, Samsung $; Canon's nanoimprint; AI chips under scrutiny; $10T data center buildout; $1.5B SiC boost; chip smuggling; 800V power; quantum HW scales up; mobile fab... semiengineering.com/chip-ind…
#semiconductor #semiEDA
Semiconductor Engineering retweeted
The shift from software-defined to AI-defined vehicles raises questions about whether the hardware can keep up.
semiengineering.com/ai-defin…
#automotive #SDVs #AIdefinedvehicles
Semiconductor Engineering retweeted
Increasing power density makes heat, stress, and aging harder to predict, and more critical to address earlier in the design. Part 2.
semiengineering.com/thermal-…
#semiconductor #photonics #thermal #AIchips
Semiconductor Engineering retweeted
The imec report: Towards scalable sCFET standard cell architectures: split-gate devices, a 5T+1 CFET SRAM bit cell, and improved back-end-of-line routability [Part 2] semiengineering.com/advancin…
#CFETs @imec_int #semiconductor #sCFETs #mCFET #SRAM
Semiconductor Engineering retweeted
Specialization and orchestration are becoming more important as the role of AI agents in chip design widens, but coordination, control, and trust remain challenging semiengineering.com/when-ai-…
#semiEDA #AgenticAI #chipdesign #semiconductor
Semiconductor Engineering retweeted
SE's new eBook, Photonics Fundamentals for Electronics Engineers, explores the technologies pushing optical data movement from racks toward packages & closer to where data is processed — and what engineers need to know as that shift accelerates
semiengineering.com/photonic…
#photonics
Semiconductor Engineering retweeted
As models evolve faster than silicon cycles, chip architects must balance flexible compute, data movement, and defense-in-depth security.
semiengineering.com/the-hidd…
#EdgeAI
Semiconductor Engineering retweeted
Chip Industry Week In Review semiengineering.com/chip-ind…
Autonomous workflow design; CFETs push scaling beyond 10Å; physical AI; new Spectre-v2 attack; photonics moves closer to compute; quantum HW; false base station risks; 88k engineers; memory test...
Semiconductor Engineering retweeted
Chip Industry Technical Paper Roundup
semiengineering.com/chip-ind…
#semiconductor #gpus #hardwaresecurity #AgenticAI #semiEDA #rowhammer #PDN
Semiconductor Engineering retweeted
Latest: AI agents move deeper into chip design; China doubles down on AI compute/memory; supply chains tighten; TSMC partners accelerate; ICs head to space; optics advances, neural super resolution, auto PQC; Purdue-UIUC workforce training semiengineering.com/chip-ind…
#semiconductor
Semiconductor Engineering retweeted
Redundant feeds protect uptime, but they also strand capacity that could support more hardware. semiengineering.com/ai-data-…
Semiconductor Engineering retweeted
Thermally induced warpage, caused by differences in the rate at which materials expand when heated, is becoming problematic in large chips/packages. semiengineering.com/negative…
#semiconductor #warpage #NTE #CTE
@mcgc_en @AmkorTechnology @brewerscience
#advancedpackging @Synopsys
Semiconductor Engineering retweeted
New technical papers recently added to Semiconductor Engineering’s library
semiengineering.com/chip-ind…
#semiconductor #3DIC #chiplets #BEOL #thermalmodeling #semiEDA #neuromorphiccomputing #LLMs
Semiconductor Engineering retweeted
The difficulty in building a package digital twin goes beyond creating accurate electrical, thermal, or mechanical models. semiengineering.com/why-pack…
#semiconductor #advancedpackaging #digitaltwins #chiplets #semiocnductormanufacturing
Semiconductor Engineering retweeted
Robotics and AI are taking on more tasks in fabs today, particularly to reduce unscheduled downtime and ensure more good wafers are produced with existing capacity.
semiengineering.com/how-robo…
#semiconductor #fabs #robotics




