Burrito technologist. @AMD Infinity Fabric performance and architecture. CTRL+ALT+DEL the GOP. Personal account. Reluctant x86 defender.

Vancouver, British Columbia
Joined November 2008
My BIL’s name is Moise, but I only call him by his full name of Modified Owned Invalid Shared Exclusive when he’s in real trouble.
M(O)ESI(F|R) Modified, Owned, Exclusive, Shared, Invalid, Forward, Recent Coherency protocol states for a given line in a modern microprocessor cache
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“Testifying in a court case where Qualcomm is suing Arm, CEO Cristiano Amon said that the San Diego firm actually reached out to Intel at one point in an attempt to license x86.” 👀 xda-developers.com/qualcomm-…
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Phil Park retweeted
Just a normal day in British Columbia.
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Phil Park retweeted
Approaching A 10 Second Linux Kernel Build Incredibly wild with latest @AMD @AMDServer and pending Linux patches, now possible to build default x86_64 kernel right now in 15 seconds! Hoping Venice will cross 10! phoronix.com/review/near-10-…
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Replying to @philparkbot
I have Genoa
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Neat. It’s a Turin EPYC 9D25
The Meta Muse computer is real! Told ya. "I’ve seen a couple of posts about this so wanted to demystify. Today, every Muse user gets a free computer in the cloud. It's a real computer" "Just as you can when you install Linux on your home computer, you can poke around and see all the files that make the system work - both debian system files and the binaries and data files that implement the parts of Muse" "your Muse Secure VM truly is your own computer in the cloud. You can install software in it, write and compile code, use the browser to surf the web: it is your own Linux box that you can operate as you choose with your Muse." "We’re really proud to be able to put a real computer in millions of people’s hands with a similar level of transparency." "when you ask your Muse to show you its entire filesystem, and receive gigabytes of files you’re seeing the full contents of the runtime cell."
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Phil Park retweeted
Agentic AI is changing what CPUs need to deliver. Hear AMD CTO Mark Papermaster and Mike Clark, Senior VP, Corporate Fellow and Chief Architect of AMD CPUs, discuss why optimizing for both thread density and strong single-core performance matter for the next era of AI: bit.ly/4h7Jig1
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Interesting perspective; this is more of a culture/management issue. The red flag is anyone using the phrase, “Claude said so.” At best they’re more like junior engineers or interns. You should be telling them what to do, not the other way around! reddit.com/r/ECE/s/5q41wSC9s…
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I’m reminded of this @ernstdj post where he noted that DRAM cost per bit has been flat for over a decade. We’ve been building DRAM capacitors vertically but the aspect ratio is hard to increase with diminishing returns on density. Now we have MCR and higher HBM stacks, but
No one talks about how the DRAM density curve has basically…flattened. Maxed-out Server 2021: 8TB Ram Maxed-out Server 2026: …also 8TB Ram That’s insane! A five-year stagnation. If your working set exceeds 8TB, tough luck! Quite literally the only thing that’s going to get us exponential again is alternative tiers of memory. Specifically, ones that don’t rely on CPU memory controllers. This is why I’m constantly rambling about CXL. Sure, there’s a latency cost, and a smart programmer will have to treat it differently. …but are you not excited? We’re entering the heterogenous memory era (again)! Imagine hundreds of terabytes of RAM on a single server! Absolutely insane to think about.
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DRAM is starting to consume a higher share of power as we add more capacity. Managing refresh becomes another interesting problem to solve. Anyway fun times ahead.
I remind people of this often: I started doing JEDEC work in 2013 and the price/GB has been effectively the same the whole time. ...and sadly a lot of the players still seem to think the old model holds!?!
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I was writing an email about something uarch related and as I wrote, “last data beat pick” Outlook autocomplete suggested “last data beat pickleball”, which is a word I have never typed before prior to this post. Never change, Outlook
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an ISA can not "theoretically deliver performance", it's literally just an ISA. performance relies on the actual microachitecture implementation. c'mon man!
RISC-V、理論上は性能出るはずなのに、実チップの性能はARMに及ばないのは何でだろう。私が知らないだけか?
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My life right now
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Phil Park retweeted
It's been a while since I've had the opportunity to do a GPU deep dive. So it is nice to get back to it. AMD provides plenty to talk about with CDNA 5. The shift to Wave32 has been a long time coming, and the memory subsystem is wild. It's going to be an interesting chip.
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Phil Park retweeted
Everyone's trying to make CPUs faster. I’m trying to make them worse. New project: CPU deoptimization. Searching for the slowest possible machine instructions x86 single instruction record: 198,002,498,236 cycles, 62 seconds The assembly hall of shame: github.com/xoreaxeaxeax/asm-…
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Hello. Zen 5 (and soon Zen 6) is where AVX-512 runs the best. chipsandcheese.com/p/zen-5s-…
we gotta stop the avx512 larping guys. no it is not beautiful, and no it is not peak efficiency. here's a plain C++ implementation, that beats the avx512 version, running SEVEN TIMES faster using just avx2: godbolt.org/z/jxGvM4n8f (tested on a 10k$ xeon, supposedly where avx512 runs best!) to make it even funnier, this "beautiful" avx512 version also introduces a correctness issue trashing nearby pixels as soon as you pass transparent points, see: pasta.can.ac/ukigoxenec.py Zig has a beautiful integration of LLVM vector operators, why do this yourself?
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My first report from @AMD Advancing AI event last week (another report on edge coming shortly). AMD announced its new MI455 GPUs, new rack Helios, new customer @AnthropicAI and a disaggregated inference solution with @cerebras: eetimes.com/warning-shots-fi…
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This was clever. A professor gave a writing assignment and then put in a Van Halen/brown M&Ms clause to see who used AI without checking the paper. 32/35 failed.
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