@geschema

FPGA wizard at @PLC2GmbH, software developer, dad and guitar rookie. Natural health enthusiast. Creator of https://xitter.cf/t.co/T4N9bTQl4S. Opinions are my own.

 Marckolsheim, France
noasic.com
Joined December 2008
  • Tweets1.4K
  • Following75
  • Followers956
107Media
Guy Eschemann retweeted
Dr Sarah Myhill@MyhillNews5 Dec 2023
Please donate to my GMC Judicial Review Fighting Fund. See dailymail.co.uk/news/article… Please donate to Sarah Myhill Limited Sort code 20 61 08 Account number: 50760242 Many thanks, Sarah
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I want to have gone into my doctor’s office at my college 19 years ago, when I felt like I had a fever.. See a specialist, get diagnosed with some condition and have them give me a bunch of those marvelous shiny color brochures… New post on my blog: whitneydafoe.com/mecfs/?post…

The Gods Must Be Crazy

I want to have gone into my doctor’s office at my college 19 years ago, when I felt like I had a fever, and I want to actually have had a fever, instead of a low temperature…get diagnosed with some...

whitneydafoe.com
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The latest version of @Sigasi Studio can warn you about forgotten reset values in clocked VHDL processes. Such a useful feature! insights.sigasi.com/releasen…
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The people over at fpgainsights.com asked me a few questions about #FPGA design. You can read the full interview here: fpgainsights.com/guy-eschema…
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We're delighted to provide the McMaster Interdisciplinary Satellite Team (MIST) at McMaster University in Canada with free airhdl.com subscriptions to support the development of their nanosatellites! mcmasterneudose.ca/ mcmasterneudose.ca/supporter…
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A sometimes overlooked metric in Xilinx #FPGA designs is the number of unique control sets—a control set being defined as the combination of a clock, a clock-enable and a reset signal. Too many control sets prevent the efficient packing of logic into slices.
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Xilinx recommends to keep the number of unique control sets below 7.5 % of total slices to avoid impacting timing and placement. In Vivado, you can query the number unique control sets in your design using the "report_control_sets -verbose" command.
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Optimize your RTL code down to an acceptable number of logic levels, based on the rule of the thumb above. (3/4)
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As a last resort, use out-of-context synthesis to compile the troublemakers with special options. (4/4)
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When it comes to #FPGA timing closure, it's a good idea to keep an eye on the number of logic levels in your design. In Xilinx (oops, AMD) Vivado you can do this using: report_design_analysis -logic_level_distribution -extend Do it post synthesis to save time! (1/4)
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Use rules of the thumb, such as 500 ps per logic level, to estimate whether your design has a chance to work at the target clock frequency. (2/4)
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A public service reminder to always keep your #FPGA logic under reset while its clock-generating circuit (PLL or MMCM) is not locked. This is especially important for stateful logic like FSMs.
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A good teacher makes me feel like I can fly; a bad teacher gives me the feeling that I'm not smart enough.
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Guy Eschemann retweeted
airhdl@airhdl28 Feb 2023
New blog: Using airhdl to Design a PN Sequence Checker for an Analog Devices ADCs airhdl.com/blog/2023/02/27/u…
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Working on 64-bit support for @airhdl. This has been requested a lot recently. Will be available soon to subscribers of the Professional plans.
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Working on a HIL test setup for @airhdl. From now on, as an additional safety net, every code generator update will go through a HIL test to make sure that the generated code actually works in hardware. #FPGA #AXI4 #VHDL #SystemVerilog
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We're adding volatile register fields to @airhdl. Those will get their write-value from the bus, and their read-value from the user logic. Useful for reading out a timer value and setting it to a new value through a single register (e.g. for time synchronization applications).
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A good read: DDR4 SDRAM - Understanding the Basics systemverilog.io/ddr4-basics

DDR4 Tutorial - Understanding the Basics - systemverilog.io

DDR4 SDRAMs are very prevalent in devices that use ASICs and FPGAs. In this tutorial we explore the basics of DDR4 memory starting with what it looks on the inside, how basic operations such as READ...

systemverilog.io
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Guy Eschemann retweeted
Jim Lewis@SynthWorks2 Nov 2022
Be sure to vote in Aldec's FPGA User Survey 2022 and log your vote for your favorite FPGAs, your favorite FPGA design and verification language (such as VHDL), and your FPGA verification methodology (such as OSVVM) resources.aldec.com/acton/fo… #FPGA #VHDL #OSVVM
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Guy Eschemann retweeted
airhdl@airhdl18 Sep 2022
New Generator: Linear-Feedback Shift Registers airhdl.com/blog/2022/09/18/n…
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