VHDL Verification Specialist, OSVVM author, VHDL Trainer, Yogi
Joined April 2009
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Jim Lewis retweeted
Online Advanced VHDL Verification Training Courses - September - mailchi.mp/firsteda.com/upco…
Jim Lewis retweeted
Been working on an SPI to AXI4-Lite bridge recently. A beta version is now available on GitHub: github.com/airhdl/spi-to-axi…
Thanks to @SynthWorks and @Sigasi for helping out.
Join me on Thursday's webinar to learn about how OSVVM's Advanced VHDL Verification Data Structures simplify their usage.
osvvm.org/archives/2012
Join me at our upcoming webinar to learn how OSVVM has created simulator independent scripting and best in class test suite and test case reports.
osvvm.org/archives/2008
#vhdl #verification #osvvm
Instructor lead, on-line VHDL classes from VHDL expert and IEEE VHDL Standards WG Chair. Details at: synthworks.com/public_vhdl_c…
With our "half day" on-line format, we do on-line classes right. #vhdl #osvvm #verification
It is great to see Aldec's good support of the VHDL-2019 standard. It is nice to see the hard work of the IEEE 1076 Working Group pay off. Having spent 1000's of hours on this effort myself, I am grateful to Aldec for implementing this.
Advancing VHDL's Verification Capabilities with VHDL-2019 Protected Types design-reuse.com/news/51669/… #semiEDA @AldecInc
Jim Lewis retweeted
Lately, me and @unaimarcor worked on github.com/pyTooling/Actions to simplify #githubactions for #Python projects. It supports: unit testing (#pytest), code coverage, static type checking (#mypy), packaging, publishing to PyPI, test reports and Sphinx documentation on GH pages.
ALT Example workflow testing and packaging a Python project and publishing tagged versions to PyPI.
VHDL+OSVVM 2021.10 Functional Coverage Reports
Now the big difference between #vhdl+OSVVM vs SystemVerilog+UVM functional coverage reporting is the cost. OSVVM is free (#foss) and only requires a basic VHDL-2008 simulation license.
Full article is here: osvvm.org/archives/1897
OSVVM 2021.10: Build Summary Reports
When we run a set of tests, we need to be able to assess whether all test cases passed or quickly identify which test cases failed.
Full article is here: osvvm.org/archives/1879
#vhdl #osvvm #verification #foss #opensource
OSVVM & UVVM: Differences and Unification
Currently OSVVM and UVVM are largely duplicating what each other is doing. This a waste of time and resources.
Lets unify and work together: osvvm.org/archives/1864
#osvvm #uvvm #vhdl #verification
VHDL+OSVVM are great for verification - especially FPGA verification. When you use OSVVM appropriate patterns, VHDL+OSVVM compares well to SystemVerilog+UVM. #osvvm #vhdl
linkedin.com/pulse/vhdlosvvm…
Jim Lewis retweeted
This is pretty much what the rest of the world thinks about American🇺🇸 health care. We have no idea why you put up with, it just looks insane to the rest of us. You're all nuts! 🤷♂️
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Jim Lewis retweeted
To all the VHDL people out there, do you now about IEEE-P1076.gitlab.io? That's the site of the VHDL Analysis and Standardisation Group (VASG). We are gathering and organising Bug Reports and Capability/Feature Request for the next revision of the language (202X). Come by!
One can never get enough on metastability and synchronization
Interesting papers by R. Ginosar wrt metastability and safe synchronization in hardware design:
"Fourteen ways to fool your synchronizer" webee.technion.ac.il/people/… 10.1109/ASYNC.2003.1199169
"Metastability and Synchronizers: A Tutorial" webee.technion.ac.il/~ran/pa… 10.1109/MDT.2011.113
Join the second #Webinar in the #VHDL-2019: Just the New Stuff series. The focus will be on Protected Type Enhancements and Verification Data Structures. See linkedin.com/pulse/vhdl-2019…
VHDL-2019: Just the New Stuff
Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment
linkedin.com/pulse/vhdl-2019…
