An open-source RISC-V out-of-order processor
Berkeley, CA
Joined January 2016
- Tweets426
- Following36
- Followers2.7K
- Likes102
Pinned Tweet
BOOM hits a new milestone! Read about the new v3, SonicBOOM! Slightly higher IPC in SPECint17 and Coremark relative to the A72s in AWS Gravitonv1! Appearing virtually at the next CARRV workshop, this Friday May 29th. (carrv.github.io/2020/papers/…). 💥
The BOOM Processor retweeted
News flash: Esperanto Technologies Partners with Intel to Advance Massively Parallel RISC-V-based AI Acceleration Solutions! #Intel #riscv #AI #ML #semiconductors @esperantotech @risc_v esperanto.ai/News/esperanto-…
The BOOM Processor retweeted
Intel, welcome to the @risc_v Revolution!
Today @Intel declares their support for RISC-V, further igniting cultivation of opportunity and collaboration across industries. Together we have the power to change the course of history. Welcome Intel as a premier board member of @RISC_V!
riscv.org/whats-new/2022/02/…
The BOOM Processor retweeted
Currently enjoying teaching Agile Hardware Design, and we are happy to open-source all of our materials & lecture recordings: classes.soe.ucsc.edu/cse293/…
VLC just added some patches to support the recently minted RISC-V Vector spec! Super cool! (via redd.it/slei7b)
The BOOM Processor retweeted
FireSim 1.12 and Chipyard 1.5 Released! Check 'em out.
github.com/firesim/firesim/r…
github.com/ucb-bar/chipyard/…
The BOOM Processor retweeted
Hotchips 2021 advance program online now! @hotchipsorg Hear @EsperantoTech Chairman and Founder Dave Ditzel @DaveDitzel speak on "Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip" August 24. hotchips.org/advance-program…
Pretty neat to see this stuff listed on wikichip, although it is a little Spartan at the moment. 🤔 T0 and Rocket especially deserve more attention. en.wikichip.org/wiki/uc_berk…
The BOOM Processor retweeted
AI news! Esperanto Unveils ML Chip with Nearly 1,100 RISC-V Cores at the RISC-V Summit December 8, 2020. In HPCWire. @EsperantoTech @riscv_a @risc_v #ML #AI #DL hpcwire.com/2020/12/08/esper…
Super exciting news: "Esperanto Technologies to Reveal Chip with 1000+ Cores at RISC-V Summit!" (spoiler alert: I (Chris) worked on ET-Maxion, which is BOOM-derived💥!) @EsperantoTech news.ycombinator.com/item?id… esperanto.ai/esperanto-techn…
The BOOM Processor retweeted
Getting the traditional #HotChips2020 experience with a hot California summer and an ice cream bar for final break :)
The BOOM Processor retweeted
I reverse-engineered the register file in the Intel 8086 microprocessor. Each register cell is static, based on two inverters in a loop. Some registers are multi-ported, more complexity than I expected in a 42-year-old processor.
righto.com/2020/07/the-intel…
ALT Die photo of the 8086 microprocessor with the registers highlighted. There are seven 16-bit upper registers, 6 bytes of instruction prefetch queue, and eight 16-bit general-purpose lower registers.
ALT A closeup of a multi-ported register cell, showing the silicon and polysilicon structures. The schematic of the cell is next to the photo. It has three bit lines and 5 control lines: three for reads and two for writes.
ALT The die of the 8086 microprocessor stripped down to the silicon to show the transistors. The lower registers are highlighted and an inset image zooms in on this circuitry. A single register cell is highlighted with an inset showing a closeup of the cell.
ALT The upper register file is a matrix of register cells: 16 wide for 16 bits and 10 high for 10 registers. Different registers have a slightly different design.
Many of you have been asking us for the source code to SonicBOOM! We can now officially point you to the BOOMv3 GitHub release (concurrent with Chipyard v1.3). Get the links and read the change log at: groups.google.com/d/msg/risc…
Of course, we don't just do the occasional code-drop; if you want bleeding edge changes, you can always see the latest commits at (github.com/riscv-boom/riscv-…). Caveat Emptor, of course. =)
Incremental compile for HW simulations & synthesis!! But now how am I suppose to schedule my coffee breaks?
This Post is from an account that no longer exists. Learn more
New SonicBOOM features include auto-predication of short forward branches, a multi-load load/store unit, a TAGE-L (loop) predictor, RVC compressed support, RoCC co-processor support, and a FireSim/FPGA+Dromajo ISA model checker for verification (Fromajo 🧀)!
The BOOM Processor retweeted
Happy Birthday, @risc_v ! 10 years old today! What an incredible first decade it's been - thanks to the whole community for bringing us along this far:
riscv.org/2020/05/happy-10th…