Editor In Chief of Semiconductor Engineering #semiconductor #semiEDA #AI #embedded #verification #lowpower #test #DataAnalytics #automotive #ICmanufacturing #ML
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Joined April 2013
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Semiconductor Engineering's latest special report
semiengineering.com/why-phys…
#PhysicalAI #AgenticAI #humanoids #robotics
Synopsys CEO Sassine Ghazi talks about AI agents, the limits of autonomous engineering, digital twins, and the challenges facing 3D-ICs.
semiengineering.com/how-clos…
#semiEDA #chipdesign #AgenticAI @Synopsys
#autonomouschipdesign #3DIC
Latest: Fab expansion accelerates; China advances memory & EUV; Teradyne’s test deal; SEMICON West & OCP highlights; 3D SiP; TSMC & ASML signals; 300mm fab $; optical and 3D-compute startups funding; quantum HW... semiengineering.com/chip-ind…
#semiconductor #semiEDA
Agentic workloads increase CPU demand, while reasoning models, MoE architectures, and reservoir computing fuel AI acceleration.
semiengineering.com/agentic-…
#GPU #CPU #AgenticAI #semiconductor
Streaming sensor data creates new challenges for advanced process control. semiengineering.com/shift-le…
#semiconductor #fabs #semiconductormanufacturiong
Startup Funding: Q3 2026
semiengineering.com/startup-…
80 startups raised $8.5B in Q3, with big hauls by companies tackling data movement and memory.
#startups #AIhardware #semiconductor #semiEDA
#photonics #quantum #startupfunding
Latest: $2B foundry pact; hyper-NA EUV; TSMC, Samsung $; Canon's nanoimprint; AI chips under scrutiny; $10T data center buildout; $1.5B SiC boost; chip smuggling; 800V power; quantum HW scales up; wireless EV road charging; mobile fab... semiengineering.com/chip-ind…
#semiconductor
CPO Testing Faces A Moving Target Problem:
Test vendors are adapting to changing connector architectures and extreme alignment tolerances as co-packaged optics heads toward mainstream. semiengineering.com/cpo-test… #CPO #CPOtest #semiconductor #datacenters #NPO #copackagedoptics
Extreme Environments Push Chips To Their Breaking Point semiengineering.com/extreme-…
Orbital data centers, defense systems, quantum computing, particle physics, and advanced manufacturing are raising the bar for simulation, test, and lab tools.
#semiconductor
Ed Sperling retweeted
The imec report: Towards scalable sCFET standard cell architectures: split-gate devices, a 5T+1 CFET SRAM bit cell, and improved back-end-of-line routability [Part 2] semiengineering.com/advancin…
#CFETs @imec_int #semiconductor #sCFETs #mCFET #SRAM
Ed Sperling retweeted
As models evolve faster than silicon cycles, chip architects must balance flexible compute, data movement, and defense-in-depth security.
semiengineering.com/the-hidd…
#EdgeAI
Chip Industry Week In Review
semiengineering.com/chip-ind…
Autonomous workflow design; CFETs push scaling beyond 10Å; physical AI; new Spectre-v2 attack; photonics moves closer to compute; quantum HW; false base station risks; 88k engineers needed.
#semiconductor
Ed Sperling retweeted
SE's new eBook, Photonics Fundamentals for Electronics Engineers, explores the technologies pushing optical data movement from racks toward packages & closer to where data is processed — and what engineers need to know as that shift accelerates
semiengineering.com/photonic…
#photonics
Chip Industry Technical Paper Roundup
semiengineering.com/chip-ind…
#semiconductor #gpus #hardwaresecurity #AgenticAI #semiEDA #rowhammer #PDN
Specialization and orchestration are becoming more important as the role of AI agents in chip design widens, but coordination, control, and trust remain challenging.
semiengineering.com/when-ai-…
#semiEDA #AgenticAI #AIagents #SLMs #chipdesign #semiconductor
Ed Sperling retweeted
Latest: AI agents move deeper into chip design; China doubles down on AI compute/memory; supply chains tighten; TSMC partners accelerate; ICs head to space; optics advances, neural super resolution, auto PQC; Purdue-UIUC workforce training semiengineering.com/chip-ind…
#semiconductor
Ed Sperling retweeted
📅 Our next #LinkedInEvent happens Oct. 6! Join Synopsys SVP Prith Banerjee and @SemiEngineering's @Chip_Insider for a conversation on the current state of multi-die design and the challenges shaping its adoption across the semiconductor industry. Register now: bit.ly/4AzfLDB
As AI chips move to stacked, chiplet-based architectures, EDA vendors are reworking mature tools for cross-domain analysis, faster exploration, and agentic AI assistance.
semiengineering.com/3d-chips…
#semiEDA #3DIC #semiconductor #chipdesign
Ed Sperling retweeted
New technical papers recently added to Semiconductor Engineering’s library
semiengineering.com/chip-ind…
#semiconductor #3DIC #chiplets #BEOL #thermalmodeling #semiEDA #neuromorphiccomputing #LLMs
Ed Sperling retweeted
Robotics and AI are taking on more tasks in fabs today, particularly to reduce unscheduled downtime and ensure more good wafers are produced with existing capacity.
semiengineering.com/how-robo…
#semiconductor #fabs #robotics
