Moved to https://xitter.cf/t.co/s8sZ4LI6W0
Cambridge, MA
Joined January 2011
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Finally, a proper "pip/npm for hardware", major SiliconCompiler upgrade, SiliconCompiler.com .
Try it!
import siliconcompiler
import umi # design
chip = siliconcompiler.Chip("top.v)
chip.use(umi) # pulls in dependencies
# your code
chip.run()
Get ready for the post Moore wafer-scale era. Check out our latest paper showing RTL simulation of a million cores processor. (RISC-V) arxiv.org/abs/2407.20537
We just open sourced Logik, our light weight Python based FPGA toolchain. No more TCL and 100GB binary blob downloads! Please try it,we are proud of this work.🙏
github.com/zeroasiccorp/logi…
$ python -m pip install --upgrade logik
This post shows how to build and verify your own chip(let) in Python. Writing SV testbenches is not fun, Switchboard and SiliconCompiler improves life quality! 😉Try it out and let us know what you think.
zeroasic.com/blog/ebrick-dem…
If you haven't tried SiliconCompiler yet, you really should;-) Convert Verilog to GDS in one line.
$ pip install siliconcompiler
$ sc <yourmodule>.v
We have decided to open source "switchboard", the powerful low latency communication library at the core of our emulation platform. It may look easy, but it's not.
github.com/zeroasiccorp/swit…
zeroasic.com/blog/switchboar…
We have open sourced our "Universal Memory Interface" protocol for chiplets. Includes a complete reference implementation. Spread the word.🙏 github.com/zeroasiccorp/umi
Hi old friend! Zero ASIC came out of stealth today to launch the ChipMaker ASIC design and emulation platform. I can almost guarantee that you have never seen anything like it. Try it out and let me know what you think! zeroasic.com