Working on a series of new routines specialized for writing the contents of the 4x4 XMTRX active matrix registers into destination matrices stored within memory which have been over-aligned to 32 bytes, or the size of a single cache line on the Sega Dreamcast’s SH4 CPU. This bad boy foregoes prefetching the destination cache lines with the PREF instruction, as is done for regular matrix alignment, and instead preallocates them using the MOVCA.L instruction before writing to them, which should eliminate a shitty pipeline stall that occurs on the SH4 when issuing a write with a prefetch in-flight. The gist of the approach is guaranteed to be quite gainzy over prefetching with only the default 8-byte alignment requirements, but… I cannot be sure that I’ve played an optimal round of SH4 ASM Tetris, hand-scheduling instructions to reduce pipeline stalls and maximize dual dispatch, until I get to my DC and profile this mofo using the cycle-accurate SH4 performance counters… 🤔