@pulp_platform

A joint effort of @ETH_en, University of Bologna @Unibo + partners for Parallel Ultra-Low Power computing. Boldly designing open hardware since '13.

pulp-platform.org
Joined February 2016
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You can now find and download Marco's PhD thesis "Many-Core Programmable Clusters for Open, Software-Defined, and AI-Native Radio Access Networks" in the ETH Zurich Research Collection: research-collection.ethz.ch/… @MarcoBertuletti
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We are delighted to introduce our new colleague Yuhan! Yuhan will be focusing his research on MAGIA platform integration and deployment for AI models. His research interests include computer architecture and AI accelerator design. Welcome to the team!
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We are excited to present Thomy, the first chip we made with an openPDK ICsprout55. Check out asic.ethz.ch/2026/Thomy.html & github.com/openecos-projects….
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Greetings from #CERN where we have Viviane and Jayanth attending the workshop on Brevitas to dive deep into neural network quantization!
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You can now find Yichao's PhD thesis " Toward Thousand-Core Shared Memory: Scalable Many-Core Architectures for Data-Intensive Workloads" in the Research Collection of ETH Zurich: research-collection.ethz.ch/… @yichao_zh
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Cédric, Marc-Andre & Sebastian recently participated at #IUS2026 in Raleigh presenting their work on wearable ultrasound. Check out their papers arxiv.org/abs/2610.01602, arxiv.org/abs/2610.06263, arxiv.org/abs/2610.01603, arxiv.org/abs/2610.01623. Have a great weekend!
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Kai & Chen recently attended #BEC2026 taltech.ee/en/bec2026 in Tallinn, meeting with our partners from TalTech & TAICHIP, sharing their research. Kai presented 'PULP4SPACE: Developing Next-Generation Space Processing Platforms' at the TAICHIP special session.
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Our new colleague Glenn recently attended #MICCAI2026 in Strasbourg where he presented "S-CEReBrO: Breaking the Memory Barrier in Continuous EEG Monitoring". Check out his paper here: arxiv.org/abs/2607.27913
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A quick look back at the conference panel "AI as the Chip Designer: Evolution or Illusion?" that took place at #VLSISoC in Cyprus with Frank representing PULP. See vlsi-soc.com/program.html#pa… for details.
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And here is Lorenzo who presented his work "Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip" at #VLSISoC in Cyprus. Find the poster and slides here: pulp-platform.org/docs/vlsis… pulp-platform.org/docs/vlsis…
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