san francisco
Joined December 2015
- Tweets2.3K
- Following873
- Followers3.4K
- Likes14.3K
emilio andere retweeted
we’re partnering with @youdotcom to bring Wafer’s inference to developers through its new Inference Router.
access Wafer through one OpenAI-compatible API, with multi-provider failover and built-in web search from You.com.
link in thread 🧵
Introducing Inference Router: enterprise-grade inference on demand.
Kimi K3, GLM 5.3, DeepSeek V4.1 Flash, Qwen3.8 Flash, Muse Spark 1.3, Mercury 3 and more, available with an uptime SLA of at least 99.9%. US hosting and web search built in.
you.com/router
emilio andere retweeted
we’re partnering with @youdotcom to bring Wafer’s inference to developers through its new Inference Router.
access Wafer through one OpenAI-compatible API, with multi-provider failover and built-in web search from You.com.
link in thread 🧵
Introducing Inference Router: enterprise-grade inference on demand.
Kimi K3, GLM 5.3, DeepSeek V4.1 Flash, Qwen3.8 Flash, Muse Spark 1.3, Mercury 3 and more, available with an uptime SLA of at least 99.9%. US hosting and web search built in.
you.com/router
emilio andere retweeted
Introducing Inference Router: enterprise-grade inference on demand.
Kimi K3, GLM 5.3, DeepSeek V4.1 Flash, Qwen3.8 Flash, Muse Spark 1.3, Mercury 3 and more, available with an uptime SLA of at least 99.9%. US hosting and web search built in.
you.com/router
emilio andere retweeted
we’re powering token pass on @vercel 🤝 @wafer_ai
available as an add-on to vercel pro. more models coming soon
vercel.com/docs/ai-gateway/t…
emilio andere retweeted
DeepSeek V4.1 Flash 1017 is now included in Vercel Token Pass.
• New weights from DeepSeek
• 1M context window
• No config change
Get $80 of tokens for $30/mo ↓vercel.com/changelog/deepsee…
emilio andere retweeted
excited to partner with @Vercel to power Token Pass!
for $30 per month, your team gets $80 in monthly credit for:
- GLM 5.3,
- Kimi K3
- DeepSeek V4.1 Flash 1017
powered by Wafer, with more models coming soon!
available as an add-on to Vercel Pro.
links in thread 🧵
emilio andere retweeted
DeepSeek v4.1 Flash (1017) is now included in ▲ Token Pass.
Fast, mind-bogglingly cheap, and served with ZDR (zero-data retention).
It's a phenomenal model to run subagents that execute plans conceived by larger and more expensive models. You can port TypeScript to Rust 10 times and not run out of credits 😂
DeepSeek V4.1 Flash 1017 is now included in Vercel Token Pass.
• New weights from DeepSeek
• 1M context window
• No config change
Get $80 of tokens for $30/mo ↓vercel.com/changelog/deepsee…
emilio andere retweeted
Another takeaway after three years of building a company is that the returns to just "being a good person", and not acting transactionally, are higher than I expected.
There are so many transactional, boring, and at times immoral people in the tech industry that if you act with sustained warmth, authenticity, humor, and integrity, great gifts will be laid before you. White pill.
emilio andere retweeted
If you build an automation machine, the way to monetize it is to sell it to as many people as possible -- anyone who has tasks to automate.
But if what you build is an invention machine, then the best way to monetize it is to use it yourself.
emilio andere retweeted
huge updates coming to the gpu perf engineering repo
what resources are we missing?
we're doing a massive update on Wafer's popular open source guide to GPU performance engineering!
a few cool resources going into this update:
⠀
1. Stream-K: why a matmul can leave part of the GPU idle while the last blocks finish, and how dividing the multiply-accumulate work more evenly helps.
⠀
2. tcgen05 for dummies: gau-nernst builds a Blackwell matmul step by step. Tensor Memory, asynchronous copies and pipelining, with code you can follow as the kernel develops.
⠀
3. Thinking Machines' Defeating Nondeterminism: how changing the batch can change the order of floating-point additions, and why that can change inference results. then, how to make the kernels batch-invariant.
⠀
4. Triton's Linear Layouts: how tensor elements are arranged across threads and registers, and the data movement needed to change that arrangement.
⠀
the update also expands the quantization, speculative decoding and hardware references.
⠀
the guide starts with one inference request, then moves through GPU fundamentals, kernels, serving engines and distributed systems. start at the beginning if you're new; use the individual sections when you hit a specific problem.
⠀
if you know a primary source that explains one of these topics better, open a PR.
emilio andere retweeted
we're doing a massive update on Wafer's popular open source guide to GPU performance engineering!
a few cool resources going into this update:
⠀
1. Stream-K: why a matmul can leave part of the GPU idle while the last blocks finish, and how dividing the multiply-accumulate work more evenly helps.
⠀
2. tcgen05 for dummies: gau-nernst builds a Blackwell matmul step by step. Tensor Memory, asynchronous copies and pipelining, with code you can follow as the kernel develops.
⠀
3. Thinking Machines' Defeating Nondeterminism: how changing the batch can change the order of floating-point additions, and why that can change inference results. then, how to make the kernels batch-invariant.
⠀
4. Triton's Linear Layouts: how tensor elements are arranged across threads and registers, and the data movement needed to change that arrangement.
⠀
the update also expands the quantization, speculative decoding and hardware references.
⠀
the guide starts with one inference request, then moves through GPU fundamentals, kernels, serving engines and distributed systems. start at the beginning if you're new; use the individual sections when you hit a specific problem.
⠀
if you know a primary source that explains one of these topics better, open a PR.
emilio andere retweeted
Blackwell Tuning Guide is required reading for ai perf engineers
it covers register limits, thread-block clusters, distributed shared memory, shared-memory carveouts, L2 persistence, and NVLink peer access.
follow and save to keep up with the series. links in thread 🧵
we launched the most comprehensive ai performance engineering repo in the world
we're posting every single resource
follow and save to keep up with the series. links in thread 🧵
part 14: Blackwell Tuning Guide
NVIDIA covers the execution limits, memory hierarchy, and communication mechanisms behind tuning AI workloads on Blackwell:
- register budgets, resident warps, and occupancy in fused AI kernels.
- shared-memory limits for attention and matmul tiles across Blackwell compute capabilities.
- thread-block clusters and distributed shared memory for exchanging tensor data across blocks.
- 8-block portable clusters, B200's optional 16-block clusters, and the parallelism tradeoff of larger clusters.
- L1/shared-memory carveouts and the balance between caching and explicit tensor staging.
- L2 cache persistence for inference kernels that reuse the same tensors.
- NVLink peer access and direct tensor transfers between GPUs in model-parallel inference.
the guide connects Blackwell's hardware limits to kernel design decisions like tile size, block cooperation, and tensor reuse, helping engineers choose what to test when tuning attention, matmul, and multi-GPU inference.
emilio andere retweeted
we launched the most comprehensive ai performance engineering repo in the world
we're posting every single resource
follow and save to keep up with the series. links in thread 🧵
part 14: Blackwell Tuning Guide
NVIDIA covers the execution limits, memory hierarchy, and communication mechanisms behind tuning AI workloads on Blackwell:
- register budgets, resident warps, and occupancy in fused AI kernels.
- shared-memory limits for attention and matmul tiles across Blackwell compute capabilities.
- thread-block clusters and distributed shared memory for exchanging tensor data across blocks.
- 8-block portable clusters, B200's optional 16-block clusters, and the parallelism tradeoff of larger clusters.
- L1/shared-memory carveouts and the balance between caching and explicit tensor staging.
- L2 cache persistence for inference kernels that reuse the same tensors.
- NVLink peer access and direct tensor transfers between GPUs in model-parallel inference.
the guide connects Blackwell's hardware limits to kernel design decisions like tile size, block cooperation, and tensor reuse, helping engineers choose what to test when tuning attention, matmul, and multi-GPU inference.
emilio andere retweeted
you'll know more about GPU memory access and kernel optimization than 96.76% of people if you fully understand the CUDA C++ Best Practices Guide
it covers profiling, memory coalescing, shared-memory bank conflicts, register use and occupancy, transfer overlap, and checking outputs against a reference. AI engineers can apply these when choosing tensor layouts and validating kernel changes.
follow and save to keep up with the series. links in thread 🧵
we launched the most comprehensive ai performance engineering repo in the world
follow and save to keep up with the series. links in thread 🧵
part 12: CUDA C++ Best Practices Guide
NVIDIA's guide helps AI performance engineers connect a slow training step or inference request to a change they can test. it's a reference for deciding whether to change a tensor layout, reduce data movement, or tune a kernel's resource use.
NVIDIA covers the measurement and optimization decisions behind CUDA applications:
- profiling representative workloads and using Amdahl's law to estimate the benefit of accelerating a hotspot. for inference, use relevant batch sizes and sequence lengths to decide which kernels deserve engineering time.
- timing GPU work with CUDA events and comparing requested memory traffic with actual transfers. for tensor copies and layout conversions, these measurements help check how much bandwidth the access pattern wastes.
- keeping intermediate tensors on the GPU between model operations to avoid CPU round trips. pinned host memory and separate non-default streams can overlap incoming transfers with independent computation when the hardware supports it.
- coalescing global-memory accesses by matching thread assignment to tensor layout. for strided tensors and transposes, inspect which addresses neighboring lanes touch before choosing a new layout or writing a custom kernel.
- reusing matrix tiles in shared memory to reduce repeated global loads. the guide's transposed-tile example shows how padding removes its bank conflicts, giving engineers a concrete layout change to evaluate inside tensor kernels.
- balancing block size, registers, and shared memory when tuning custom AI kernels. more registers can reduce spilling while lowering occupancy, so measure runtime across configurations to decide whether that tradeoff helps.
- checking numerical results after changing reduction order or using faster math functions. for custom normalization or softmax kernels, compare outputs against a reference with explicit error tolerances alongside performance measurements.
the worked matrix multiplications connect memory access patterns to measured performance. use them to plan a kernel optimization, then check whether the change improves the full training or inference workload while preserving numerical accuracy.
emilio andere retweeted
we launched the most comprehensive ai performance engineering repo in the world
follow and save to keep up with the series. links in thread 🧵
part 12: CUDA C++ Best Practices Guide
NVIDIA's guide helps AI performance engineers connect a slow training step or inference request to a change they can test. it's a reference for deciding whether to change a tensor layout, reduce data movement, or tune a kernel's resource use.
NVIDIA covers the measurement and optimization decisions behind CUDA applications:
- profiling representative workloads and using Amdahl's law to estimate the benefit of accelerating a hotspot. for inference, use relevant batch sizes and sequence lengths to decide which kernels deserve engineering time.
- timing GPU work with CUDA events and comparing requested memory traffic with actual transfers. for tensor copies and layout conversions, these measurements help check how much bandwidth the access pattern wastes.
- keeping intermediate tensors on the GPU between model operations to avoid CPU round trips. pinned host memory and separate non-default streams can overlap incoming transfers with independent computation when the hardware supports it.
- coalescing global-memory accesses by matching thread assignment to tensor layout. for strided tensors and transposes, inspect which addresses neighboring lanes touch before choosing a new layout or writing a custom kernel.
- reusing matrix tiles in shared memory to reduce repeated global loads. the guide's transposed-tile example shows how padding removes its bank conflicts, giving engineers a concrete layout change to evaluate inside tensor kernels.
- balancing block size, registers, and shared memory when tuning custom AI kernels. more registers can reduce spilling while lowering occupancy, so measure runtime across configurations to decide whether that tradeoff helps.
- checking numerical results after changing reduction order or using faster math functions. for custom normalization or softmax kernels, compare outputs against a reference with explicit error tolerances alongside performance measurements.
the worked matrix multiplications connect memory access patterns to measured performance. use them to plan a kernel optimization, then check whether the change improves the full training or inference workload while preserving numerical accuracy.
emilio andere retweeted
Hiring for Members of Technical Staff to work on rigorous evaluation of AI in biology.
Our mission is to advance humanity's ability to engineer biology. We approach this by understanding and improving AI’s application to biology across basic research, drug discovery, and biosecurity. We are a team of engineers, scientists, and operations specialists who are driven by improving capabilities and interpretability. Some of our work is showcased on benchmarks.bio.
About this role
You’ll turn your understanding of a biological domain into a roadmap of benchmarks and design them with engineers. Then build and manage your own scientific team using your network and internal talent infrastructure.
You have
(1) deep scientific expertise and experience using AI tools
(2) or strong coursework in math/CS and experience working with scientists
This is a high-intensity, founder-type role. Our Members of Technical Staff have built companies, run drug programs and scaled complex technical projects.
Projects you might work on
- Design benchmarks with engineers and scientists, from selecting scientific questions and datasets to developing reliable graders.
- Work with engineers on large-scale computing and AI inference infrastructure to evaluate models and investigate their failures.
- Research new methods for evaluating scientific capabilities and measuring improvements from training.
- Work with our internal data generation and drug development teams to build tasks around real experiments and research decisions.
How we work
Our MTS team works in person in Mission Bay, San Francisco. We keep meetings to a minimum and are flexible about when you arrive or leave. Tight deadlines and customer commitments sometimes require late hours.
Our work in use
Frontier AI labs use our benchmarks to assess biological capabilities and safeguards. Our work appears in research announcements and model cards, including:
- anthropic.com/claude-fable-5…
- anthropic.com/claude-opus-5-…
- anthropic.com/news/healthcar…
- media.x.ai/v1/website/card4p…
- x.ai/news/biosafety-at-the-f…
Hiring Process
Our process is typically completed within two weeks.
- Round 1: Introduction
- Round 2: Technical project matching
- Round 3: Take-home evaluation project (~2 hours)
- Round 4: Technical interview / live engineering session (1 hour)
- Round 5: Paid onsite project and presentation (2–3 days) - Offer
Compensation & Benefits
- 350K-500K+ OTE
- Equity
- Unlimited PTO
- Health, dental and vision insurance fully covered
- Visa sponsorship and relocation assistance
- 401(k)
- Office in Mission Bay, San Francisco
- Lunch and dinner provided
Apply at jobs.ashbyhq.com/latchbio/9b…. Or send an email to kenny[at]latch[dot]bio
