RISC-V RTOS-enabled multi-core SoC using Wishbone4 Interconnect.
Joined July 2012
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Also coming in the next release:
I added SPI flash support for all supported FPGAs, enabling larger apps beyond the 256 KB block RAM limit found on most of them.
I am also developing a bootloader to load apps from SPI flash or an SD card, which will restore Linux boot support.
Coming in the next release:
Last week, I redesigned the SD-card controller, moving it from hardware to software.
This makes it easier to enhance with multi-block operations for faster transfers.
The new design supports SPI or 4-bit SD mode and uses 70% fewer hardware resources.
I also added a bare-metal SD-card test app for both throughput benchmarking and data integrity testing.
- The old controller let timed writes complete before the card fully received/programmed the block, likely explaining figures above 50 Mbps.
I’m working with Claude to add GDB `load` support to the underLineOS GDB stub, turning it into a binary loader as well.
This means switching programs will no longer require the expensive bitstream regeneration and flashing cycle.
