"if i had a nickel for every time i accidentally found a zero click RCE, i'd have two nickels, which isn't a lot but it's weird that it happened twice" she/her

Berkeley, CA
Joined April 2020
Replying to @ImogenBits
if i take your hand and you take mine, we'll both be locked together till the all mighty kernel above decides to strike us both down 💞
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If you are interested in uArch Security, we just opened an internship position at @Apple! The position is focused on offensive research, and you will be contributing to the security of some of our most advanced CPUs in one of the coolest teams. Apply at: jobs.apple.com/en-us/details…
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First big result from our new CPU research project, a use-after-free in AMD Zen2 processors! 🔥 AMD have just released updated microcode for affected systems, please update! lock.cmpxchg8b.com/zenbleed.…
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MD5 (absolutely_not_a_ppl_bypass.txt) = a332a9a9c87136ec1615b9af701c171a
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it's incredible what sorts of bugs you can find while procrastinating on studying for finals lol. coming soon to a product-security@ near you :)
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Little late on reading this paper, but throughly enjoyed it :) tldr: some CPUs use the BHB to index the BTB to improve accuracy. If you massage the BHB, you can hit any other same context entry in the BTB to cause a misprediction to your choice of preexisting target. /1
Spectre-v2 is back! Disclosing Branch History Injection (#BHI/#Spectre-BHB), bypassing Spectre-v2 hw defenses to leak arbitrary kernel/host memory (e.g., root password hash below). Joint work by @enrico_barberis @pit_frg @nSinusR @herbertbos @c_giuffrida: vusec.net/projects/bhi-spect…
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It's neat seeing how even the smallest user taint of predictor structures can come back to bite you. I also really appreciated the discussion on exploitability when eBPF is unavailable—too many papers take unprivileged access to a kernel JIT for granted when it is rare indeed /2
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I am somewhat curious why AMD and some of Arm's cores didn't see similar issues; using BHBs to make BTB entries context sensitive seems like a natural choice (ie a previous type check correlated with the indirect target). Maybe it's not as helpful as I imagine? Too expensive? 3/3
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guess who has two thumbs, a kernel fuzzer, and a MacBook that no longer boots? it's me!! at least the screen did a cool thing before it completely conked out 😭🤡
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I don't know what I hit but it hangs on boot with no signs of life. Guess it's DFU time, never fuzzing my personal hardware ever again lol
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Allison Husain {@[email protected]} retweeted
Replying to @SCOTUSblog
The justices now can join the citizens in not trusting the Court.
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free awful idea: are you worried about other CPUs/bus agents in your system scribbling on your code and hijacking your kernel? simple! fault your code into the L1I$ and then turn off CPUECTLR_EL1.SMPEN to make your core fully incoherent/ignore cross-core cache ops 🥲
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and, jokes aside, this is super cool because you can use this to build an OS on commodity hardware that is resistant against an adversary with full physical memory R/W (assuming they compromise after your core booted) since you can authenticate any data you load/store from RAM
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there are also some fun small hacks you can make for specific cores like the A53 where SMPEN also makes the L1D$ incoherent and so you can just treat the D$ as secure data memory. The A53 has a pLRU policy for L1$s so you don't even have to do anything evil to make it work :)
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I think whatever slight difference that has is largely irrelevant since while the 4% CPU performance gap is acceptable, the 25% memory burden is not. They also ran tests in C using real PAC instructions so it seems like they at least did their due diligence here
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(it's not 3 actually, misread the table. It looks like 6 integer FUs are available to xor, which might be an actual problem for their methodology given the sheer size of the reorder buffer)
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me: hey xcodebuild, can u compile this project for me please? xcodebuild: best I can do is heap corruption and crash me: understandable have a nice day
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Today we present deep research from our @wipawel into the branch predictor of AMD CPUs and abusing its behavior to exploit Spectre v1 much more easily than previously understood, culminating in reproducing an arbitrary kernel mem leak PoC in only 3 days. grsecurity.net/amd_branch_mi…
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ARM friends: does anyone know what SCTLR.UMA is actually useful for? It lets EL0 control interrupt masking, which seems like a universally unwise thing since then user space could just turn off interrupts and hog a core forever. Is this a hack for RTOSs? who wanted this so bad??
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I'm using it to do micro user space context switches but I cannot for the life of me figure out why this feature exists in the first place since it clearly wasn't meant to do this lol
Replying to @ezhes_
I don't know what you'll do with this information, but I'm using it to build a terrifying toy OS which shares one page table between all processes and just protects the other process' memory on ctx switch instead of switching tables. It actually works but it feels 100% illegal.
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just accidentally broke my personal record of most ":)" in a short email. who knows, maybe that third smiley was the really important one which correctly conveys that i didn't mean to be confrontational 🙃
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