@chipflow_io

Helping product companies to make their own chips

chipflow.io
Joined October 2021
  • Tweets40
  • Following7
  • Followers267
3Media
🎉🎉🎉 lnkd.in/e-SNzMW9
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Check out the @chipflow_io very early alpha! We are dedicated to building the best user experience possible to build custom ICs. It’s early days and *your* input is important.
ChipFlow@chipflow_io21 Dec 2022
Try our tutorial and see how easy our new tools make it to build and test custom SoCs! #ASIC support coming soon! docs.chipflow.io/en/latest/t…
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ChipFlow retweeted
YosysHQ@YosysHQ15 May 2023
In this great post by @y__ we follow his journey of implementing a #RISCV CPU with Amaranth #HDL. Some great background on using #FPGAs for science, and his challenges and successes while following @BrunoLevy01 's excellent Blinker to RISCV guide. blog.yosyshq.com/p/blinker-t…
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#TinyTapeout 3 closed on Monday, and I've been putting together the statistics and getting the datasheet built. We had 100 submissions (25% from universities) and I filled the remaining space with 149 designs submitted to TinyTapeout 2.
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EU #chips act has been agreed! Exciting times for #semiconductor #transformation in Europe. lnkd.in/dqBQ_VfC

EU legislators strike deal on €43B chips plan | Rob Taylor

EU #chips act has been agreed! Exciting times for #semiconductor #transformation in Europe.

linkedin.com
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OpenUK
@openuk_uk14 Mar 2023
Watch @robtaylor78 CEO of @chipflow_io's talk: "A Chip on my Shoulder" at State of Open Con 23 #SOOCon23 #opensource #OpenHardware ow.ly/xyx350N9SNI
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This week @robtaylor78, CEO of @chipflow_io joins me from #stateofopencon #SOOCon23 to chat about about the intersection between open source software design and hardware design and more. The Business of Open Source: emilyomier.com/podcast/rob-t…

Bringing Hardware Design to The Software Space at The State of Open Con with Rob Taylor of ChipFlow...

In the first of my series of interviews from the State of Open Con in London, I’m chatting with Rob Taylor, CEO of ChipFlow , about the intersection between open source software design and hardware...

emilyomier.com
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We are happy to announce @Google as a sponsor for @LatchUpConf in Santa Barbara, CA March 31 to April 2! Thank you for your support of free and open source silicon. For more information about the event, visit latchup.io Catch up at Latch-Up!
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It's Valentine's day, so let's bring some love to you all with a new edition of El Correo Libre fossi-foundation.org/ecl/ecl… This time we have the new FOSSi toolchain from @QuickLogic_Corp, @mhosseinaskari's NNA called BARVINN, @antmicro's NVMe ML accelerator and much more. Enjoy!
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Time to try a very high resolution stitch of the National NS32032 microprocessor...
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OpenUK
@openuk_uk7 Feb 2023
.@robtaylor78, CEO at @chipflow_io, will be taking us on a journey, setting out the history of this rapidly growing ecosystem of open source semiconductor design and the commercial applications. Head to the Open Hardware room now!
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YosysHQ@YosysHQ6 Feb 2023
New guest post by @suarezvictor and @pipelinec_hdl! In this article we present a tool flow that takes C++ code describing a raytraced game, and produces digital logic that can be implemented in off-the-shelf #FPGA with no hard or soft CPU used. blog.yosyshq.com/p/3d-raytra…
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In this tutorial you'll learn how to build, simulate and extend a custom #RISCV SoC using the Amaranth #HLS language. docs.chipflow.io/en/latest/t…
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And thanks to @matthewvenn for helping me prepare some of the content! Have a look at his Zero to ASIC course and the Tiny Tapeout project if you are looking for a guided way into the world of ASIC development.
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Great to see so many people interested in Free and Open Source Silicon at #FOSDEM2023! fosdem.org/2023/schedule/eve… will have the slides and the recording soon. If you haven't done so, subscribe to El Correo Libre (fossi-foundation.org/ecl) to keep in touch with the community.
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My first ever paper was accepted to ISCAS 2023. It's a fully opensource neuromorphic chip. Download the paper: arxiv.org/abs/2302.01015 Checkout the repository: github.com/sfmth/OpenSpike Special thanks to @mguthaus and @jasoneshraghian, co-authors of this work.
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In this tutorial you'll learn how to build, simulate and extend a custom #RISCV SoC using the Amaranth #HLS language. docs.chipflow.io/en/latest/t…
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This week @matthewvenn of the Zero To ASIC Course returns to The Amp Hour to talk about what has been happening in the world of #OpenSource #Silicon, both the tools that make things go and the projects that people are creating. buff.ly/3R2nLGN
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Place and Route is the #ASIC terminology of the week! zerotoasiccourse.com/termino… In the last month, Place and Route has been the 18th most popular out of 42 terms.

Place and Route

Place and route are two automated ASIC design steps that position standard cells on the die and then connect them with wiring on the metal layers to produce the final physical layout.

zerotoasiccourse.com
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Everyone says the Intel 8086 processor has 29,000 tiny transistors. But I counted and found 19,618. Why the difference? It turns out that most counts include "potential" transistors as well as real ones. Let's take a look and find out why.🧵
A detailed die photo of the 8086 microprocessor. The metal layer has been removed to show the silicon underneath.

ALT A detailed die photo of the 8086 microprocessor. The metal layer has been removed to show the silicon underneath.

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