Verification methodology by day. Author and open-source developer by night. All opinions my own.
Joined December 2018
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Matthew Ballance retweeted
WOSET is next Thursday (11/03/22). Free virtual registration lots of great open source EDA talks.
woset-workshop.github.io/
I think a big question for me is how this syntax composes into something bigger. I get (after some explanation) the adder. What about the equivalent of 2k lines of RTL? Hopefully it’s more RTL-like than gate level
What tool are you using to generate the program? I’m familiar with riscv-dv, but it sounds like you’re using something else.
Not sure what your doc system is, but there do seem to be Python and Sphinx wrappers: pypi.org/project/bit-field/ pypi.org/project/sphinxcontr…
While I haven't used it for a project, bitfield has always looked interesting: github.com/wavedrom/bitfield
Matthew Ballance retweeted
Accellera will host an online workshop to discuss the parallelization of #SystemC simulations on 7 April 2022. The workshop is free but registration is required. lnkd.in/gMbEyf4C
Excellent session packed with tons of actionable approaches to improve the verification planning and execution process!
Matthew Ballance retweeted
GDBWave - A Post-Simulation Waveform-Based RISC-V GDB Debugging Server tomverbeure.github.io/2022/0…
ALT Flow chart that shows the different steps in using GDBWave: simulating RTL, launching gdbwave, launching a RISC-V GDB, debugging the simulated CPU.
ALT Diagram that shows the difference in complexity between the full stack from debug IDE to CPU in a traditional embedded CPU environment, and the minimal stack that's required by GDBWave.
Just tried @TIDAL tonight. Thus far, it’s pretty good. Noticeably better audio quality!
If you’re thinking about adding transaction viewing to your VCD viewer that would be very interesting.
Matthew Ballance retweeted
chipIgnite one - up and running in seconds. It is using Caravel with clock mesh patch to address timing issues with metal only changes.
This will enable use cases such as creating a sequence-class instance in Python and passing it to SV to run on a UVM agent. Most important, it should make adding Python to a TB an incremental step. Stay tuned, I expect to begin writing about it soon (in the next month or so)!
I'm currently working on (and have been for about a year) a more ambitious framework to enable simulation-centric cross-calling between languages such as SystemVerilog and Python.
Much of the performance hit in my experience is due to cocotb integrating at the signal level (vs procedure level), and not due to Python itself.