Thank you to everyone who attended the first-ever @hackerfabindia × @archgen_ session on semiconductors design and fabrication at LocalHost HQ last week! More than 50 people joined us to explore how open-source initiatives such as openROAD and the Open-Source FPGA Foundation are helping democratize custom semiconductor design and fabrication. A special thank-you to @aryamman_bhatia for taking time out of his incredibly busy schedule to explain how people can build their own fabs, even without cleanrooms, massive capital investments, or traditional infrastructure. Huge thanks as well to @suhasasumukh for hosting us at @localhostIND. @naveen_venk and I had a fantastic time discussing open-source chip design and sharing how Archgen AI is helping grow the community through our agentic EDA systems. #Semiconductors #OpenSourceEDA #ChipDesign #HackerFab #VLSI #AgenticEDA

@naveen_venk and I had an awesome chat with @aryamman_bhatia about how chip design can be made more accessible and open. Would love to share some of our learnings over coffee tomorrow on how you can build your own semiconductor chip. Do register!! @archgen_ @hackerfabindia

Got a chance to host @aryamman_bhatia at @lossfunk. We talked about what it'll really take to design and fabricate cutting edge semiconductors from india

What an awesome crowd @lossfunk!!

On our way to @lossfunk to talk about how to use AI to design better semiconductor chips!!!

We built the best chip design engine in the world!! 🥳🥳 @archgen_ is currently ranked #1 on the @WeAreHRT / Partcl Macro Placement Challenge 2026 leaderboard. Macro placement is one of the hardest problems in physical design. It involves placing large fixed-size blocks such as SRAMs, IPs, and analog macros on a chip floorplan while balancing, wirelength, density, congestion, routability, timing and constraints. After months of research and iteration our submission reached a verified rank-1 with an average proxy cost of 0.9507 across the IBM benchmark suite. @naveen_venk and @JishnuMada86596 burned the midnight oil to build an optimization flow that combined fast local repair, multi-start search, congestion-aware ranking, GPU-accelerated candidate generation and strict legality checks to reach the top spot. (detailed blog in the comments) Grateful to Madhusudan S, Abhishek Lal, and Anant Gulati for their valuable suggestions and inputs to help us overcome issues in EDA algorithms, traditional macro placement algorithms and GPU optimisation. If you are working on physical design and want to understand how AI, self learning agents, loops, and GPU-accelerated optimisation can improve your flows please feel to reach out to us. Thank you @Willschips, Vamshi Balanaga and the Partcl team for organising this competition. #PhysicalDesign #EDA #ChipDesign #VLSI #AIforEDA #Semiconductors #Placement #ArchGen #HardwareDesign

Thrilled to announce that @naveen_venk and I have joined @join_ef to build @archgen_ . Our thesis is simple: The next generation of semiconductor design tools will not just automate workflows they will learn from every engineer who uses them. Chip design today is full of repeated manual effort. 1. A senior physical design engineer fixes a timing issue. 2. Another engineer solves a congestion problem. 3. Someone else discovers a better macro placement strategy. 4. A team spends weeks tuning PPA across hundreds of experiments. But most of this knowledge disappears into scripts, logs, webex threads, reports, and individual engineer's memory. We’re changing that. At @archgen_ , we’re building self-learning agents for semiconductor design, with specific focus on physical design. Our agents work alongside engineers, run EDA flows, inspect reports, debug failures, optimize PPA, and capture the reasoning behind successful workflows. 1. When an engineer solves something, the agent learns. 2. When a strategy fails, the agent remembers why. 3. When a similar problem appears again, the agent can reuse the right approach. Over time, this becomes an organisational memory layer for chip design. One that compounds. Our vision is to make chip design feel less like manually stitching together fragmented tools and more like working with a team of expert agents that get better every day. The future of semiconductor design is self-learning. Huge thanks to @suhasasumukh 🐐 and @localhosthq for being extremely generous with their credits and supporting us throughout. #semiconductors #EDA #physicaldesign #ASIC #chipdesign #AI

Our paper on Privacy Preserving Load Forecasting via Federated Learning just got published!!🥳🥳 Personalized AI for energy is finally leaving the centralized silo. Your home’s power data doesn't have to live in a utility’s database to be useful. We show how to train high-accuracy load models across thousands of smart meters without ever moving the raw usage data. Instead, it ships "noisy" model updates and keeps the personal habits local. It's not just keeping data private, it’s making the model actually better by letting it learn your specific routine. When a utility predicts power demand, it usually needs to see exactly when you turn on your dryer or AC. That is a massive privacy risk. High-res meter data is basically a map of your life. The conventional fix is Federated Learning (FL), where the model goes to the data. But standard FL has a "heterogeneity" problem, it struggles because every house uses power differently. Our paper introduces DP-SA-FedPer: an architecture that solves the privacy-utility-efficiency trilemma. Differential Privacy (DP): It adds mathematical "noise" to model updates so no one can reverse-engineer your habits from the weights. Secure Aggregation (SA): The server only sees the total sum of updates, never an individual household’s contribution. Lightweight Personalization: The model is split. A global "base" learns general grid trends, while a local "head" stays on your meter to learn your specific 2 AM laundry habit. > 95.2% Accuracy (outperforming standard centralized models). > 12% lower communication cost than baseline FL. > 6.5% boost specifically from the personalization layer. Privacy isn't a tax on performance anymore. By combining secure aggregation with local "heads," we can build a grid that is more efficient, more scalable, and respects the front door. @naveen_venk @archgen_

Thank you soo much @agupta, @snowmaker and @xuster for putting together the first ever startup school in India! @archgen_ is building AI agents to accelerate semiconductor chip design and has some awesome numbers to back our macro placement engine. Would love to get 5 min of your time to share more.

Lessgoo @ycombinator startup school!! @archgen_ is building ai agents for designing semiconductor chips, would love to catch if you're around.

Thank you so much to the @OpenAIDevs team for giving us this opportunity to show what AI can do for silicon design! Huge shoutout to @harshitm29 @gabrielchua @reach_vb for putting together this fantastic event 🙌 #CodexBLR