The recording of the #UALinkConsortium panel from #OCPSummit26 is now available. Watch the panel featuring @AMD, @Synopsys, @asteralabs, @MicrochipTech, and @intel to learn how to scale AI with #UALink: youtu.be/5CB8z45zMrY
In-Network Compute in the #UALink Common Specification 2.0 helps reduce communication overhead, improve accelerator utilization, and enable more efficient AI #ScaleUp architectures. Read the #UALinkConsortium blog to learn more: bit.ly/4oTS0Rf
Watch the latest #UALinkConsortium webinar to explore the latest #UALink specifications, including In-Network Collectives, Management and Chiplet specifications, and what they mean for scalable AI infrastructure: bit.ly/4i24ODA
#UALinkConsortium is scoping #UALink 3.0, focusing on 400G data rates, optical interconnects, end-to-end resiliency, and richer management features. Read the blog to learn what’s next for UALink: bit.ly/4gHtLSv
Join the #UALinkConsortium “Powering AI at Scale: Inside the UALink Ecosystem" panel today at the #OCPSummit26 to discuss real-world #UALink use cases. Learn more: bit.ly/3TTpfJn
Missed the #UALinkConsortium Breakfast Briefing at #AIInfraSummit? Watch the recording to hear how the latest #UALink specifications and a growing ecosystem are shaping open AI #ScaleUp: youtu.be/H87VoGKlaWs?si=b5xx…
Join the #UALinkConsortium at the #OCPSummit26 for the "Powering AI at Scale: Inside the UALink Ecosystem" panel, where experts from @AMD, @Astera Labs, @Intel, @Microchip, and @Synopsys will discuss real-world #UALink use cases. Learn more: bit.ly/3TTpfJn
What if the network did part of the work? The #UALinkConsortium blog, “Exploring In-Network Compute: How #UALink Is Redefining AI #ScaleUp Architecture,” explores in-network compute, which runs reductions and sync in flight inside the fabric. Learn more: bit.ly/4oTS0Rf
Heading to #OCPSummit26? Join the #UALinkConsortium panel, "Powering AI at Scale: Inside the UALink Ecosystem," featuring speakers from @AMD, @AsteraLabs, @intel, @MicrochipTech, and @Synopsys. Learn more: bit.ly/3TTpfJn
At #OCPAPACSummit2026 #UALinkConsortium, members @AMD, @AsteraLabs, @MicrochipTech, and @Synopsys break down how the #UALink ecosystem is driving performance, power efficiency, and interoperability across disaggregated AI compute pods. Learn more: bit.ly/4rqg931
Don't miss tomorrow's breakfast briefing at #AIInfraSummit: “Building the Future of AI Scale-Up,” with speakers from AMD, Astera Labs, Google, and Microchip on the growing UALink ecosystem. Learn more: bit.ly/4xxL93x
#AIInfraSummit is this week! Visit the #UALinkConsortium at Booth no. 737 to see two live demos from @Cadence and @Synopsys. Learn more about #UALink activities: bit.ly/4xxL93x
Help shape the future of open, high-performance AI #ScaleUp connectivity.
Join the #UALinkConsortium and collaborate with industry leaders advancing an open ecosystem for next-generation AI infrastructure.
Become a member today: bit.ly/45873hb
Join #UALinkConsortium at #AIInfraSummit for a breakfast briefing with experts from AMD, Astera Labs, Google, and Microchip about the growing ecosystem behind #UALink technology. Learn more: bit.ly/4xxL93x
#UALinkConsortium members are developing the foundational #UALink technologies needed to support the next generation of #AIInfrastructure. Read our latest blog to learn what’s coming in the UALink 3.0 specification and stay ahead of what’s next: bit.ly/4gHtLSv
Visit the #UALinkConsortium (Booth no. 737) at #AIInfraSummit to see live demonstrations from @Cadence and @Synopsys highlighting the technologies advancing open, interoperable scale-up connectivity for AI infrastructure. Read our blog to learn more: bit.ly/4xxL93x
Read the “Building the Future of AI #ScaleUp: Why UALink Changes the Equation” blog to learn how #UALink combines a purpose-built architecture with an open, multi-vendor ecosystem to support cost efficiency, interoperability & supply flexibility at scale: bit.ly/49XoBj0
The UALink Chiplet 1.01 Specification is fully compliant with UCIe 3.0 and defines interfaces, form factors, flow control, and chiplet management for integrating #UALink into chiplet-based SoCs. Download the specification to learn more: bit.ly/49XwAMT
The “Open Interconnect Innovations: A Deep Dive into the UALink Chiplet Specification Tutorial presented by UALink and UCIe Consortia” tutorial is live tomorrow, Aug. 21, from 8 - 11 am PT at #HotI26!
Register today: bit.ly/4cnr4Eo
Join the #UALinkConsortium at the #AIInfraSummit to hear the latest on the #UALink ecosystem during our breakfast briefing and #ScaleUp networking panel.
Use code UALINK15 to save 15% on your ticket. Learn more: bit.ly/3QkZ4tr
