@TeamPrecisit

Software consulting company with a vision on how software engineers can be part of the newspace industry and how we can work together towards a fantastic future

 Uppsala, Sweden
precisit.se/
Joined August 2014
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#ProTip For updates on how we work, job opportunities and events, follow us on our other channels! #consultant #tech goo.gl/QcNj2L
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Four games, four small models. OnePass, our System One model, scores every legal move in a single pass: trained on MLX with ternary weights from the first step, one ONNX file, run locally on WebGPU. How they learn and measure: precisit.com/en/blog/woodpip…
Diagram: training keeps floating-point latent weights while T34 weights are used in every forward pass and shipped in one ONNX file, with int8 embedding and head and fp16 elsewhere. ONNX Runtime runs the same file as the yardstick; the browser checks size and SHA-256, loads it on WebGPU or the CPU, self-tests, and falls back to WebAssembly SIMD if the GPU self-test fails. The four latent values are illustrative.

ALT Diagram: training keeps floating-point latent weights while T34 weights are used in every forward pass and shipped in one ONNX file, with int8 embedding and head and fp16 elsewhere. ONNX Runtime runs the same file as the yardstick; the browser checks size and SHA-256, loads it on WebGPU or the CPU, self-tests, and falls back to WebAssembly SIMD if the GPU self-test fails. The four latent values are illustrative.

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One Five Dice run, 18,000 steps. Mean regret per decision falls from 0.039 to 0.0010 points, and best-move agreement rises from 93.5% to 98.6%. The logged curves are in the article's footnotes.
Five Dice training: loss over 18,000 steps with warmup and cosine decay, and validation every 2,000 steps with mean regret per decision falling from 0.039 to 0.0010 points and best-move agreement rising from 93.5 to 98.6 percent.

ALT Five Dice training: loss over 18,000 steps with warmup and cosine decay, and validation every 2,000 steps with mean regret per decision falling from 0.039 to 0.0010 points and best-move agreement rising from 93.5 to 98.6 percent.

A few spare minutes, one good game. Four in a Row, Five Dice, Reversi, Backgammon. Pick one and play: no account, no ads, no cookies, and each game works offline once played. The opponent is a small ternary model running in your browser on WebGPU. woodpip.com/
Woodpip start screen: four game cards for Four in a Row, Five Dice, Reversi and Backgammon with their pieces, the line "Classic games and a worthy opponent, a few minutes at a time", and "No account, no ads, no cookies".

ALT Woodpip start screen: four game cards for Four in a Row, Five Dice, Reversi and Backgammon with their pieces, the line "Classic games and a worthy opponent, a few minutes at a time", and "No account, no ads, no cookies".

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Curious how we built it? How a wooden games box and six values became decisions about materials, motion, levels, saved games and sharing. Designing Woodpip for a few quiet minutes precisit.com/en/blog/woodpip…

Designing Woodpip for a few quiet minutes | Precisit

A wooden games box became the starting point for Woodpip. Its materials, movements, difficulty levels and shared games grew from the same small promise: classic games and a worthy opponent, a few...

precisit.com
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If you write GPU kernels for Apple silicon, operand width is a dispatch decision, not a storage decision. Same matmul, four chips, six formats: int8 ~2x f16 everywhere, fp8 e4m3 2.08x on M6, fp4 at 1x. Every cell cites a receipt.
Precisit poster: M6 FP8 speed 2.08x, the measured rate of the fp8 e4m3 lane against the same chip's own f16 lane. Lower left: bit layout for fp4, fp8 e4m3, fp8 e5m2, bf16, f16 and f32 with elements per 32-bit word and the size of a 4096-square matrix, 8.4 MB to 67.1 MB. Right: a heat table of seven lanes across M5 Air, M5 Pro, M5 Max and M6 with the ratio to each chip's own f16 lane and absolute GOPS below - int8 1.84 to 2.35x, fp8 e4m3 1.08x, 1.04x, 0.99x and 2.08x on M6 at 29,044 GOPS, fp4 0.93 to 1.07x, f32 0.48 to 0.62x. Three rules for kernel builders at the bottom and the source repository in the footer.

ALT Precisit poster: M6 FP8 speed 2.08x, the measured rate of the fp8 e4m3 lane against the same chip's own f16 lane. Lower left: bit layout for fp4, fp8 e4m3, fp8 e5m2, bf16, f16 and f32 with elements per 32-bit word and the size of a 4096-square matrix, 8.4 MB to 67.1 MB. Right: a heat table of seven lanes across M5 Air, M5 Pro, M5 Max and M6 with the ratio to each chip's own f16 lane and absolute GOPS below - int8 1.84 to 2.35x, fp8 e4m3 1.08x, 1.04x, 0.99x and 2.08x on M6 at 29,044 GOPS, fp4 0.93 to 1.07x, f32 0.48 to 0.62x. Three rules for kernel builders at the bottom and the source repository in the footer.

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The map itself, GOPS per lane and the probe behind every number: github.com/precisit/apple-ma…

GitHub - precisit/apple-matrix-capabilities: Per-generation Apple Silicon matrix-unit capability...

Per-generation Apple Silicon matrix-unit capability map: operand formats, measured lane rates, availability constraints, and runnable probes. Evidence first. - precisit/apple-matrix-capabilities

github.com
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DeepSeek V4.1-Flash cuts KV cache to 890 bytes per token, about a quarter of V4-Flash. A full 1M-token window then costs under 1 GB of cache. It activates 16B of a 552B backbone on decode. Compression, not size, is the part that will reach small models.
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A phone where the agent is the OS, not an app on top of it. Their pitch: one entrance for apps, one for the agent. It reads the task, keeps long-term memory, decides what runs on-device and what goes to the cloud, and asks before spending your money. The future of smartphones?
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It is the first shipped attempt at an agent-native system: memory, permissions and task routing at the OS level, not a chatbot inside an app. Simple steps on-device, planning in the cloud. eu.36kr.com/en/p/40241766327…

STEPX Neo: Pioneering Intelligent Agent Future Terminals – Unlocking a New Era of Human-Machine...

Step Terminal stands out as one of the rare fully domestic independent innovators that has successfully reconstructed the complete full industrial chain, covering every critical segment from core AI...

eu.36kr.com
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Apple Silicon GPU performance on matrix-unit formats per chip (fp8/fp4/int8) AS M6 does fp8 at ~2× fp16, M5 does not. This means M6 is ~same performance as M5 Pro for GPU FP8 matrix multiplication Repo: github.com/precisit/apple-ma… Full results: github.com/precisit/apple-ma…

GitHub - precisit/apple-matrix-capabilities: Per-generation Apple Silicon matrix-unit capability...

Per-generation Apple Silicon matrix-unit capability map: operand formats, measured lane rates, availability constraints, and runnable probes. Evidence first. - precisit/apple-matrix-capabilities

github.com
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Apple M6 neural accelerator runs FP8 matrix ops at ~2× the fp16 rate, but MLX unpacks quantized weights to fp16 before multiplying. QMM (quantized matmul) staging to FP8 instead: +40% faster prefill (up to 1.5× serving Qwen3.8-27B locally)
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And same idea but on M5, where the neural accelerator fast path is integer: int8 staging for 4-bit affine weights gives ~1.4× prefill (M5 and M6)
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The story, code and evidence: precisit.com/en/blog/apple-m… Experimental MLX fork (int8 + FP8 QMM staging, not upstream yet): github.com/precisit/mlx/tree…

Small weights, fast arithmetic | Precisit

A compact model file does not determine the arithmetic a GPU performs. Measurements on M5, M5 Max and M6 show why that distinction matters for MLX prefill.

precisit.com
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MoE serving assumes NVLink. CoMoE (Tsinghua + Alibaba Cloud) makes the CPU host the routing hub: 1.46x over SGLang on RTX 5090s, 85-90% of an NVLink A800 at 23% of the cost. Macs have no P2P either. Local MoE is a topology problem. arxiv.org/abs/2610.09424

Democratizing MoE inference on commodity GPUs with CoMoE

Deploying Mixture-of-Experts (MoE) models relies heavily on Expert Parallelism, which generates intense inter-GPU communication. Consequently, state-of-the-art inference systems require...

arxiv.org
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Apple M6 adds a 2x FP8 lane to the matrix unit. We measure it at 2.1x f16 in the same harness. One catch: block scaled MX FP8 does not get it yet. The same weights through an MX scale plane run at 1.15x f16. On M6, plain per-row FP8 scaling is the door to the 2x.
Infographic: Apple M6 doubles the FP8 lane. Panel 01, the lane: fp8 e4m3 versus f16 in the matrix unit, 1.16x on M5 Air, 1.02x on M5 Max and 2.12x on M6. Panel 02, block scales do not get the lane: MXFP8 with a UE8M0 scale plane reaches 0.54x of plain fp8 on M6, 0.76x on M5 Air and 0.91x on M5 Max; per core the scaled path is flat across generations while plain fp8 doubled. Panel 03, what reaches the model: FP8 prefill against stock 4-bit on M6 is 1.37x, 1.33x, 1.31x and 1.28x at 512, 2048, 4096 and 8192 tokens, at +1.0% perplexity against +5.6% for stock 4-bit. Measured with MPP matmul2d and Qwen3-8B prefill in MLX 0.32.3.

ALT Infographic: Apple M6 doubles the FP8 lane. Panel 01, the lane: fp8 e4m3 versus f16 in the matrix unit, 1.16x on M5 Air, 1.02x on M5 Max and 2.12x on M6. Panel 02, block scales do not get the lane: MXFP8 with a UE8M0 scale plane reaches 0.54x of plain fp8 on M6, 0.76x on M5 Air and 0.91x on M5 Max; per core the scaled path is flat across generations while plain fp8 doubled. Panel 03, what reaches the model: FP8 prefill against stock 4-bit on M6 is 1.37x, 1.33x, 1.31x and 1.28x at 512, 2048, 4096 and 8192 tokens, at +1.0% perplexity against +5.6% for stock 4-bit. Measured with MPP matmul2d and Qwen3-8B prefill in MLX 0.32.3.

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One config change, 8-11% more tokens/sec. We tested fewer MoE experts per token in 4-bit Qwen3 and DeepSeek on M5 Max using MLX. Faster but quality tradeoffs varied by model. Results and reproducible code: precisit.com/en/blog/moe-exp…

Fewer experts, faster answers on a Mac? | Precisit

A one-line change makes MoE models generate faster on Apple silicon. We tested Qwen3 and DeepSeek at bf16 and 4-bit: the speed gains travelled better than the quality results.

precisit.com
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A Huawei lab open-sourced its agent model router. A small local classifier labels each request SIMPLE to REASONING; anything under your cap stays on the local model, the rest escalates. CUDA-first, no quantization path. We want that decision layer on Apple silicon.
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Repo (Apache-2.0): github.com/openJiuwen-ai/mod…

GitHub - openJiuwen-ai/model-router: OpenJiuwen model-routing kernel. Picks a model per request...

OpenJiuwen model-routing kernel. Picks a model per request with prior state snapshot. Algorithms are stateless pure functions in a swappable slot; cross-request memory is an external bounded state ...

github.com
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Best part of @huggingface's new WebGPU kernel loader is not the kernels. At startup it probes the browser with a control shader, then demotes the affected variant if the device has a known miscompile (WebKit/Metal atomics, Maxwell subgroups). Both are still unfiled upstream.
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Alibaba's chip arm is open-sourcing the fast paths for its own accelerator: PyTorch, Triton, FlashAttention and DeepGEMM ports, plus a CLI that turns CUDA code into HGGC. New silicon doesn't need a new ecosystem, it needs its fast paths ported once. github.com/t-head

T-HEAD

T-HEAD has 27 repositories available. Follow their code on GitHub.

github.com
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