SpinalHDL webinar the 16 december : datenlord.github.io/en/spina…

New #SpinalHDL documentation : spinalhdl.github.io/SpinalDo… Help yourself : Try it for your next #FPGA #ASIC project instead of #VHDL #Verilog

@3yakuya Try spinalHDL :) It's a scala library that allow you to describe your hardware without using this rock age #VHDL !

SpinalHDL is a #scala internal DSL that allow the user to remplace #vhdl and #verilog for RTL without their limitations.