@intel Why have you let the old altera.com links rot? FPGAs have long product cycles, and even obsolete parts need support. The first step to re-implementing an old design on new hardware is reproducing the design on the original hardware.
altera.com/products/boards_a…
If Intel spent a fraction of the effort they put into rebranding PDFs (don't get me started on changing the binary content of a reference PDF without revision notes) into keeping old documentation, this wouldn't be a problem.
A new ebay find arrived this week! GiDEL PROCe-III80-B with a mysterious PSDB_FIBER mezzanine board.
The PSDB_FIBER mezzanine card has a SFP cage and a camera link connector. There's also a second unpopulated SFP cage footprint.
As far as I can tell, the SFP should connect to a remote SFP-to-camera-link module.
Every time I use these port definitions, I try to read them aloud without laughing. DIPADIP... DOPADOP... BEEP BOOP
From the Xilinx RAMB36E1 port descriptions:
Here's a view of the routed board in KiCad. 4 Layers from JLCPCB. I designed the address/data busses to be pin compatible with the MC68020 board I brought up last week.
While unnecessary, I've challenged myself to route all non-power signals on two layers without vias. "This board is full of through hole parts, I shouldn't need any more holes!"
I find it is often easier to keep 5V CPLDs handy rather than a library of 7400 series logic. The complex buffering was needed to allow remapping pins to be compatible with both AS6C4008 (RAM) and SST39SF040 (Flash)
Despite being out of spec, it seems to work. This is a capture of A[15:0] clocked on TSn (transaction start)
