ALT Screen snip from README on GitHub: Building an Example SoC There is a tiny example SoC which builds on both iCEBreaker and ULX3S. The SoC contains: A Hazard3 processor, in a single-ported RV32IMA configuration, with debug support A Debug Transport Module and Debug Module to access Hazard3's debug interface 128 kB of RAM (fits in UP5k SPRAMs) A UART On iCEBreaker (a iCE40 UP5k development board), the processor can be debugged using the onboard FT2232H bridge, through a standard RISCV-V JTAG-DTM exposed on four IO pins. Connecting JTAG requires two solder jumpers to be bridged on the back to connect the JTAG -- see the comments in the pin constraints file. FT2232H is a dual-channel FTDI device, so the UART and JTAG can be accessed simultaneously for a very civilised debug experience, with JTAG running at the full 30 MHz supported by the FTDI. ULX3S is based on a much larger ECP5 FPGA. Thanks to this ECP5 JTAG adapter, it is possible to attach the guts of a RISC-V JTAG-DTM to the ...