Intel Corporation's last "Innovation Master" - the avatar is a Scientific Demon, the Intel Innovation Demon

Oregon and Travel Regularly
Joined May 2010
Richard Platt retweeted
30 nm defocus for High-NA shows serious loss of contrast (32 nm center-to-center hexagonal for 1d DRAM).
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Richard Platt retweeted
It was said here that on February 25, 2026, multiple semiconductor industry outlets reported that SMIC has successfully produced early 3-nanometer test wafers. disruptionisafactoflife.blog…
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Richard Platt retweeted
ASML Q1 2026 Earnings Call Transcript: morningstar.com/stocks/xwbo/… Customers who ordered High-NA EUV are expected to test whether it can work for real product. Thus, it's not a shoo-in. Immersion systems are ordered along with EUV systems, so DUV capacity is targeted much higher.
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Richard Platt retweeted
No defect‑free process window is observed for Metal 0 logic PnR, for any High-NA EUV dose and focus even at the 24 nm pitch. spiedigitallibrary.org/confe…
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Richard Platt retweeted
Intel/Synopsys: Buried multilayer (ML) defects in EUV masks continue to pose a significant challenge to imaging fidelity and yield in 0.33 NA EUV lithography. It's going to be even harder with High NA which can resolve smaller defects. spiedigitallibrary.org/confe…
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Richard Platt retweeted
This video summarizes the factors which fundamentally drive stochastic defectivity in EUV lithography. youtube.com/watch?v=poOhkIEx…
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Richard Platt retweeted
28 nm pitch (center-to-center) with High-NA EUV MOR has easily detected defectivity.
Replying to @lithos_graphein
Litho-eye. If you see one small contact hole there are billions of these across the chip. This is zero yield.
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Richard Platt retweeted
Restates some points I made in my EUV Substack. The stitching and die height impact on productivity also should not be ignored. If this is true customer feedback, Intel 14A may need to give up High-NA or else risk delayed acceptance. semiwiki.com/lithography/369…
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Richard Platt retweeted
Huawei's claim of 238 Mtr/mm2 density implies something like CPP=48 nm, Cell height = 175 nm, comparable to N3E or 18A, but in actuality it could be looser than N+3, just using two bonded tiers of transistors.
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Richard Platt retweeted
TSMC doesn't need to aggressively shrink any pitches going from N3 to N2 to beat Intel and Samsung at the 2nm-class transistor density. Source: youtube.com/watch?v=7m4FJm-V… (coverage starts at 5:00)
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Richard Platt retweeted
Huawei recently announced its focus on tau scaling and LogicFolding for its chip design. The claim to increase transistor density mirrors the objective of using CFETs. How could they do this with hybrid bonding? That's discussed in this article. linkedin.com/pulse/huaweis-l…
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Richard Platt retweeted
Here we examine the stochastic effects of EUV lithography for 32 nm line pitch, where, unlike metal interconnects, the lines are narrower than the half-pitch, as in DRAM word lines and bit lines. There is a significant impact on edge roughness. youtube.com/watch?v=_8fwAZCP…
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Microsoft released a set of prompts to help create a personalized AI Blueprint for your organization via @TDOttawa sco.lt/823p56
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New Report from Stanford - Evidence Base on AI in K-12: 2026 via @TDOttawa sco.lt/5gPEEy
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The invisible graveyard of AI tools in healthcare sco.lt/5OEtuq
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Cognitive Offload ... and recommendations for Education - March 2026 Research via @TDOttawa sco.lt/6pw91E
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Dario Amodei Interview: 10 Lessons on AI, Safety, and What's Coming (2026) sco.lt/7kx3my
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