
Senior Engineer @Qualcomm What makes a system well-engineered?
void*
Joined June 2024
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DRAM internals
youtu.be/7J7X7aZvMXQ?si=mARB…
The best way to learn the Windows Driver Framework (KMDF/WDF) isn't by reading endless documentation, it's by reading and understanding real sample drivers.
No amount of theory can replace the practical experience you gain from studying production-quality examples.
github.com/microsoft/windows…
> Process, threads, memory management - windows internals
youtube.com/playlist?list=PL…
GNU Compiler internals
en.wikibooks.org/wiki/GNU_C_…
Excellent resource for learning Hypervisor concepts
github.com/SinaKarvandi/Hype…
Replying to @vxunderground
Here, is the example of what you can do with PEB
metehan-bulut.medium.com/und…
I’d like to sponsor this FPGA learning kit for a deserving student who genuinely wants to learn FPGA but can’t afford it. Just a small help from my side.
@VazeKshitij @Vicharak_In, could you help me find someone who would benefit from this opportunity?
Replying to @0xpwnie
Wow. This is interesting.
Mutex objects have shared variables which are atomically updated, and based on the updated value (i.e., lock = 1 means the lock is already acquired, while a successful atomic operation acquires it with acquired semantics). So, this bug happens because while the atomic update is still in progress and its result is not yet known, the core speculatively assumes the lock will be acquired and starts executing the critical section. It may speculatively read or compute the values inside the critical section, leaving microarchitectural side effects (like cache changes), even though the execution is later rolled back if the lock acquisition actually fails.
OS Dev retweeted
Most hyperscalers have built their own Arm CPU.
Meta just asked Arm to do it themselves.
AWS has Graviton.
Oracle has Ampere.
Google has Axion.
Microsoft has Cobalt.
Huawei has Kunpeng.
Now Meta has @Arm AGI CPU.
Cloudflare is using it too.
Today @Arm announces its AGI CPU at its event.
➡️ 136 Arm Neoverse V3 Cores
➡️ Up to 3.7 GHz, 300W, TSMC N3(P?)
➡️ 2MB Private L2 Per Core
➡️ 96 x PCIe 6.0 with CXL 3.0 Support
➡️ Up to DDR5-8800, 6 TB/sec BW/core
➡️ 8160 cores per air cooled 36 kW OCP V3 Rack
➡️ Two chiplets inside
➡️ Date code 2613 on chip (ie, this week)
OS Dev retweeted
I think one of the lower level APIs will always at minimum allocate 1 byte. But that 1 byte turns into a slightly greater value based on alignment, etc.
In this case a value of 1 is treated as 0x20 from what I can tell. 0 is overridden with 1, which is then added to 0x1F. In my testing, which is simple, it is not an error and 0x20 at least for paged pool (0x20 goes in the KLFH, so we can use the traditional POOL_HEADER and not the segment heap headers). This is from nt!ExAllocateHeapPool
OS Dev retweeted
Write a C pre-processor
youtu.be/gUzPQ6kMcXo
JB
OS Dev retweeted
This work is outstanding!
arxiv.org/abs/2501.12890
OS Dev retweeted
Today's post is about generating "device clocks", used to drive interactions with external devices.
zipcpu.com/blog/2025/12/17/d…


















