As part of @sochubfi, CPC successfully taped out a customized TTA-based Digital Signal Processor (DSP). "Beaivi DSP" was fully designed and C-programmed by using the OpenASIP tools developed by the group since the 2000s: tuni.fi/cpc/headsail_tapeout… @ITC_TampereUni
The results of past 3 years of hard work on the edge AI offloading SW stack based on PoCL-R were shown in the AISA Y3 demo day last Friday. Feature showcase videos available (spoiler: Crazyflie can edge offload AI!): youtu.be/Rp6yeMuGh6s?si=o_yw… @vga_tuni @OpenCLorg @Bitcraze_se
OpenASIP v2.1 released: github.com/cpc/openasip/rele…. It adds support for LLVM 17, speeds up DSE thanks to a more intelligent LLVM BE generation, and more! @sochubfi
Customized Parallel Computing research group retweeted
Our article introduces a dual-mode processor that utilizes ILP statically when available, without suffering from low code density when it's lacking. The architecture, supported by a novel compilation method, enables fine-grained mode switching. Read more: ieeexplore.ieee.org/document…
Maarten Molendijk from @TUeindhoven presented "BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC" in @ieee_iccd. BrainTTA was designed and programmed using the openasip.org tools. tuni.fi/cpc/#BrainTTA @sochubfi
Customized Parallel Computing research group retweeted
PoCL-R is a new backend for offloading OpenCL tasks to other nodes on the network. Now with OpenCL API offloading can be performed identically whether using local or remote devices - very interesting for adaptive edge offloading and other use cases! portablecl.org/remote-backen…