@Cardyak

Computer Programmer/Hardware Enthusiast. #SiliconGang Author of CPU μarch Block Diagrams: https://xitter.cf/t.co/TsQtPgYvwW & μarch Cheat Sheet: https://xitter.cf/t.co/u17qKZbeRw

 Essex, England, UK 🇬🇧
Joined August 2009
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Inspired by @InstLatX64, today I'm introducing the #SiliconGang Microarchitecture Cheat Sheet: bit.ly/2JTplfJ This can be viewed by all, and it offers centralised information about CPU μarch design such as caches, buffers, instruction width, etc. Some notes below:
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Early Block Diagrams of the A20 P & E Core Info is tentative since most of it is grabbed from the Geekerwan review and comparing it to last years A19 model Block Diagrams: bit.ly/32qLLew μarch Cheat Sheet: bit.ly/2JTplfJ #CPU #Apple #iPhone #Tech #A20 1/4
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Hopefully the Apple Silicon Optimization guide will be updated soon to reflect these new cores📄 But regardless, by my approximate calculations: P Core: ~4% IPC increase, 16% Freq increase = 20% improvement E Core: ~27% IPC increase, 2% Freq increase = 29% improvement 3/4
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E Core now has roughly the same IPC as Firestorm, which means it's above Zen 5 (Without SMT) and Cougar Cove❄️ P Core IPC is about 45% higher than Lion Cove🔥 4/4
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Looking at the SPEC results on the Geekerwan Review for the A20 Pro, and cross referencing the relative performance of the E cores to the P core, it appears the new E cores in in the A20 Pro now have approximately the same IPC as the P core in the A14/M1 (Firestorm)
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μarch Block Diagrams: bit.ly/32qLLew μarch Cheat Sheet: bit.ly/2JTplfJ #x86 #Intel #CPU #Microarchitecture
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This is a nice trick called LoopFrog dl.acm.org/doi/full/10.1145/… Using an LLVM-based compiler to insert hints, we achieve a geometric mean loop speedup of 43%, translating to whole-program speedups of 9.5% on SPEC CPU 2017 benchmarks, with only modest area and power overheads. 1/3

LoopFrog: In-Core Hint-Based Loop Parallelization | Proceedings of the 58th IEEE/ACM International...

dl.acm.org
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LoopFrog runs multiple loop iterations from a single thread in parallel within the microarchitecture. The core can spawn future loop iterations as new microarchitectural threadlets based on compiler-inserted hints, which can leapfrog execution beyond the parent thread’s... 2/3
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...instruction window, exposing a new, medium-grained parallelism, orthogonal to traditional ILP and TLP. LoopFrog monitors data dependencies between executing threadlets, forwards data for true dependencies and squashes speculative threadlets on ordering violations. 3/3
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dl.acm.org/doi/epdf/10.1145/… "SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads" "dynamically balances ILP and TLP by executing out-of-order and in-order threads simultaneously on the same core" Could this be what AheadComputing is working on? #CPU #μarch
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dl.acm.org/doi/epdf/10.1145/… "ATR: Out-of-Order Register Release Exploiting Atomic Regions" Interesting μarch idea here. Instructions that have finished execution but not been committed yet, and also do not contain conditional branches can free up their PRF entry early #CPU #μarch
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This Gen Mobile phone SoC size
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A19Pro with A18Pro area surveying data A19Pro 与A18Pro的面积测绘数据
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Apple A19 Pro die shot Die Size 98.68mm² P-Core 2.966mm² P-Core with L2 & Shared Logic 5.486mm² E-Core 0.782mm² E-Core with L2 & Shared Logic 2.217mm² SLC 11.026mm² Somehow looks to be smaller than the A18 Pro (~104mm²) #Apple #iPhone #CPU #A19 tieba.baidu.com/p/1020632072…
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ARM's new μarches added to the block diagram repo Scarce info this year, these diagrams will be updated and mistakes corrected once more devices are released μarch Block Diagrams: bit.ly/32qLLew μarch Cheat Sheet: bit.ly/2JTplfJ #ARM #CPU #MicroArchitecture
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Nice work from @highyieldYT and also @chipwise_tech, wish we had the mm2 measurements to be able to truly compare against the A18 & A18 Pro
High Yield
@highyieldYT23 Sep 2025
.@Apple A19 SoC chip analysis based on images by @chipwise_tech: 2 P-cores with 8MB shared L2$, 4 E-cores with 4MB shared L2$, a 8-core NPU (Apple calls it 16-cores), 2x 6MB System Level Cache (SLC) and a 5-core GPU. All on TSMCs N3P and smaller than the previous A18.
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Block diagrams for A19 P & A19 E by Apple. Info sourced by Geekerwan and the Apple Silicon Optimization Guide μarch Block Diagrams: bit.ly/32qLLew μarch Cheat Sheet: bit.ly/2JTplfJ #ARM #CPU #ARM #Apple #A19 #CPU #MicroArchitecture
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The IPC for the E Core is so high now, it's only slightly behind the P Core that was present in the A12 (Vortex)
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Geekerwan's Initial Review of the A19 is out - bilibili.com/video/BV1cBp4zQ… P Core has ~12% more perf and 6% increase in IPC E Core has ~25% more perf and 17% increase in IPC If these result are accurate then the E core is simply a monster by this point. #iPhone #A19 #CPU #Apple
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Looks like Apple’s A19-E Core is 6 wide
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