if you have a high speed interface to design, like LPDDR4 or SERDES, what simulation tools do you use, and what is the baseline workflow?

@roxyallure I like your style. I'm going to bed now. I suggest you do the same ;)

@roxyallure did you just post something about twitter on facebook? I think that breaks some kind of rule.

I noticed Spartan3E has a setup/hold for it's CLBs of 210/290ps. Spartan6 has 420/280ps. is Spartan3E faster? am I missing something?

@roxyallure good stuff!

these new FPGA are rad: http://www.eetimes.com/design/military-aerospace-design/4212259/Xilinx-rad-hard-FPGA-reaches-for-the-stars